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[23.128.96.18]) by mx.google.com with ESMTP id 7si4445177ilz.34.2021.05.13.12.28.48; Thu, 13 May 2021 12:29:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233776AbhEMMNP (ORCPT + 99 others); Thu, 13 May 2021 08:13:15 -0400 Received: from mx2.suse.de ([195.135.220.15]:35436 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233782AbhEMMLZ (ORCPT ); Thu, 13 May 2021 08:11:25 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 23ACEB02C; Thu, 13 May 2021 12:10:12 +0000 (UTC) Message-ID: Subject: Re: [PATCH] cpufreq: intel_pstate: Force intel_pstate to load when HWP disabled in firmware From: Giovanni Gherdovich To: Srinivas Pandruvada , "Rafael J . Wysocki" , Viresh Kumar Cc: Len Brown , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Date: Thu, 13 May 2021 14:10:11 +0200 In-Reply-To: References: <20210513075930.22657-1-ggherdovich@suse.cz> <3fdc70c267d40561bed10fc722a8223a0b161200.camel@linux.intel.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.34.4 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2021-05-13 at 04:03 -0700, Srinivas Pandruvada wrote: > On Thu, 2021-05-13 at 12:10 +0200, Giovanni Gherdovich wrote: > > [...] > > An alternative approach to register intel_pstate in the case I'm > > describing > > would be to add ICELAKE_X (and every CPU model after that, forever?) > > to the > > list intel_pstate_cpu_ids. > > This is not nice, but unlike client server CPUs don't get released > often. There is couple of years in between. True. > > [...] > > The wording "hwp_broken_firmware" deliberately has a negative > > connotation (the > > intended meaning is: "firmware is broken, regarding HWP"), carrying > > the > > not-so-subtle message "OEM folks, please don't do this". My > > understanding is > > that the preferred way to disable HWP is with intel_pstate=no_hwp, > > the > > firmware should stay out of it. > > For me "broken" means that Intel has some bug, which is not the case, > even if the intention is to carry message to OEM. > > no_hwp is for disabling HWP even if the HWP is supported. > > The problem is that if we override the supported CPU list using some > kernel command line, some users may crash the system running on some > old hardware where some of the MSRs we rely are not present. We don't > read MSR in failsafe mode, so they will fault. We are checking some > MSRs but not all. Fair enough. > Also what will be default > (struct pstate_funcs *)id->driver_data if the cpu model doesn't match. Whoops... You're totally right, the patch I sent is broken! "id" must be a valid pstate_funcs* pointer, or some other default methods must be provided. And besides... > I think better to add CPU model instead. We did that for SKX on user > requests. ... I agree. Let's just add ICX to the list of explicitly supported CPUs. I'll send a new patch doing that, please discard this one. Giovanni