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Thu, 13 May 2021 13:38:36 +0000 Received: from DM6PR12MB3834.namprd12.prod.outlook.com ([fe80::ddb4:2cbb:4589:f039]) by DM6PR12MB3834.namprd12.prod.outlook.com ([fe80::ddb4:2cbb:4589:f039%4]) with mapi id 15.20.4129.026; Thu, 13 May 2021 13:38:36 +0000 Date: Thu, 13 May 2021 10:38:34 -0300 From: Jason Gunthorpe To: Jacob Pan Cc: Christoph Hellwig , LKML , iommu@lists.linux-foundation.org, Joerg Roedel , Lu Baolu , Jean-Philippe Brucker , Yi Liu , Raj Ashok , "Tian, Kevin" , Dave Jiang , wangzhou1@hisilicon.com, zhangfei.gao@linaro.org, vkoul@kernel.org, David Woodhouse , "Luck, Tony" Subject: Re: [PATCH v4 1/2] iommu/sva: Tighten SVA bind API with explicit flags Message-ID: <20210513133834.GC1002214@nvidia.com> References: <1620653108-44901-2-git-send-email-jacob.jun.pan@linux.intel.com> <20210510233749.GG1002214@nvidia.com> <20210510203145.086835cc@jacob-builder> <20210511114848.GK1002214@nvidia.com> <20210511091452.721e9a03@jacob-builder> <20210511163521.GN1002214@nvidia.com> <20210511110550.477a434f@jacob-builder> <20210511194726.GP1002214@nvidia.com> <20210513060012.0fcc7653@jacob-builder> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?QIVe0VNKggFK75Wy6YbUdQsCzuN+OJBorBvAU34ptqJPUozzNadV7o6CKvwc?= =?us-ascii?Q?HP5FUjxXA6lYBVEquO3ot/WmCYvLrsFP1wa7tEfh3u2Kas8dfK8gKSigeOZd?= =?us-ascii?Q?HAkgSpvRT0hIkxnn6DUq271TrzyUj5vjIGosGygNJFYFbqEoIbOrm+qDSRQ5?= =?us-ascii?Q?oKGzl30QahYsZ7Toc4iheU+MN9a4erBw10nDwbm/HKMUF0Dyf5jyJFvvOkLv?= =?us-ascii?Q?4a7Le2Jh4rNFISE+KdNHtWcchUgcX6ozJxaJYpL5SuTV6aHbz2h0oVrm7tBA?= =?us-ascii?Q?5/XnxQzjE7CBWhUw166TSEU92AQFIyJXy39e8RTwPNzA5dapSICQLAH0J/XU?= =?us-ascii?Q?sCJBIWbMypzoBo0tlzlu1eia2cmocv0ZiXpKhwMbKXINKdfRFih3R6kbR+EN?= =?us-ascii?Q?/GF2jKY+47DfKqoqTfiCF5tWq0409qlKvbxplVFTZcRo+iuMQj/Z0XWYR41Q?= =?us-ascii?Q?1PY1x1kD0G3VZAgVK92kfBvR7+SbmikH0yd9V7vghJY8KM1eTYNjOyKMoroI?= =?us-ascii?Q?fXdWdG6nC6iWqbjkZRo0MmvDVKrnpjqEFYfldBa5ayVEtNaHQlZnipAFOMrW?= =?us-ascii?Q?vLun+StAPul5/pMo5gZ4NJQhXqV87z8NmHfzFgZER5IgTHypKaOutnLmnH/o?= =?us-ascii?Q?K0UE/+sV12pf0W37mtYSBqj5nf7Mu6Za9QD/abRSFyiX42njkkiUXr7dlTw+?= =?us-ascii?Q?rGhPuIlgV2VKh6D2x2Rkja+Hmt48GlBiVYDa8Kqsny6VyG1eYTbQdp2XrM0y?= =?us-ascii?Q?fCtRI8EDJwTV3OOzKGbxzZzsGfpncjoAJfQhEutVLLHLLRZ8Bk4ChfXEHFgQ?= =?us-ascii?Q?VQIe5wee/BjwSsUnNR12lbNkj7hvjkgsg4dpy7qnlJ9POQiDsP4PagypzKfp?= =?us-ascii?Q?JiDYNt2Gbkfha5gWIw+9Kn0++L/uXqz3ANDTRblrJCs51Xk7xhevThmt8d+x?= =?us-ascii?Q?vHOAtBqarNehfzPXzEC1MHwvlZkcUd/RpIEYW0p0tdsY1gYmOUy4eGFtxg2S?= =?us-ascii?Q?WUrC/yyfMYxbrFCvS42Bur4H8rsH3pSGAjr9RJpZUI3yTz5N2YIriRMeC3K1?= =?us-ascii?Q?TLObuyxoV8vV7wjje456CMOmfqp67ev4EzKA6HizIQ1g9kyaUTsqMgvMwP7x?= =?us-ascii?Q?CoMSeIOT9KtSzvbjnvDJibXhxxWR391K6Kelygl96BQjXYv1ZCgkJHIOZtj4?= =?us-ascii?Q?KdmFvmUh/NzDLJu6L6fe4/3i166nx7nGeElopUD9NjQ5+Os+FZWkaCO0ADmQ?= =?us-ascii?Q?RagGv27IPYUgviMzOoCRgtM6UIZdcNVoGP0NJlEiY57IC5d8iiBqk2R7XRUt?= =?us-ascii?Q?VCaD8Oad5JZjsR9EK9K2aRHj?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e7425290-9b90-4e73-ab99-08d91614687e X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3834.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 May 2021 13:38:36.0223 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TjsTYvuhIxQfJsDRJLksAT9fIyr3QAQzzP5WD/YEWu4eDBtviTkvFLqOJ5lkKdFK X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1516 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 13, 2021 at 06:00:12AM -0700, Jacob Pan wrote: > > > If you want to do SVA PASID then it also must come with DMA APIs to > > > manage the CPU cache coherence that are all NOP's on x86. > > > > Yes. And we have plenty of precende where an IOMMU is in "bypass" mode > > to allow access to all memory and then uses the simple dma-direct case. > I agree it is better not to expose the entire direct map. But the missing > piece of using DMA APIs is the PASID. The caller needs the PASID value to > do work submission once buffer is mapped. You still haven't explained why the kernel driver should have a PASID at all. Jason