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Thu, 13 May 2021 22:31:24 +0000 Received: from DM6PR12MB3834.namprd12.prod.outlook.com ([fe80::ddb4:2cbb:4589:f039]) by DM6PR12MB3834.namprd12.prod.outlook.com ([fe80::ddb4:2cbb:4589:f039%4]) with mapi id 15.20.4129.026; Thu, 13 May 2021 22:31:23 +0000 Date: Thu, 13 May 2021 19:31:22 -0300 From: Jason Gunthorpe To: Jacob Pan Cc: "Luck, Tony" , Christoph Hellwig , LKML , "iommu@lists.linux-foundation.org" , Joerg Roedel , Lu Baolu , Jean-Philippe Brucker , "Liu, Yi L" , "Raj, Ashok" , "Tian, Kevin" , "Jiang, Dave" , "wangzhou1@hisilicon.com" , "zhangfei.gao@linaro.org" , "vkoul@kernel.org" , David Woodhouse Subject: Re: [PATCH v4 1/2] iommu/sva: Tighten SVA bind API with explicit flags Message-ID: <20210513223122.GV1002214@nvidia.com> References: <20210513081050.5cf6a6ed@jacob-builder> <20210513173303.GL1002214@nvidia.com> <20210513185349.GA801495@agluck-desk2.amr.corp.intel.com> <20210513190040.GR1002214@nvidia.com> <20210513192014.GU1002214@nvidia.com> <20210513124621.01421173@jacob-builder> <20210513195749.GA801830@agluck-desk2.amr.corp.intel.com> <20210513132251.0ff89b90@jacob-builder> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?5ZxretIWZgKuX74b8OM0oXU8Rcz8mFn+qMojxtrbQyCs4V9/t9rIzAfWW/Gt?= =?us-ascii?Q?/MIl/kIzjQdptgjBBSGFG5YXtUu6jtEWkFN19sg89Jy0IH65ACuST2Pvcyua?= =?us-ascii?Q?+u9dDo3uH/xuyasNGmOjrEFLzqR79mdtUxvwP5RpNXb76lqT7sP7EpOw8/wa?= =?us-ascii?Q?ljmZmM8j5VXjwABoN7gzj4ZzT1IurszSNLEXMyVDN3duYBqi1OQXnByUngLC?= =?us-ascii?Q?wYMjHlrNSmWhNutWmjHFGTB+EuGtsbv5qH9y4WtK4kS5YPPxdIqybP4JcvSL?= =?us-ascii?Q?kAT16bw39JVor2T7qixJDQLXhFCEDmDIjYACfOsMtcYTpXJuM93tuRjbkxWm?= =?us-ascii?Q?FrZlVlvqE7QlLFkqvy/Wv+rvoo2qhQoXEQKCzJpfIT9yD10ir0IcqsQ41mUy?= =?us-ascii?Q?p7tvNoR3QHU9OJZw7WlGjXzfAFOVTg4Mw1GlhqvZKZL9OlJuv4EN1nYqq4rS?= =?us-ascii?Q?NjpTdaNgNmaAsskqQH015mBYYe+KiyVCvikL7dc5+gm1bmmwYj2i70009Ybu?= =?us-ascii?Q?VJukwqkZbvecZb6kWT+Xh9J11GZUYxg521jW812I5269gJYUgVcEUI1k/nhd?= =?us-ascii?Q?cZWz43Yg4a6DuwBJ020MzBL1W/I/7ojsAW/K5Yv3VOLBWq51OdFNoo7DqEwL?= =?us-ascii?Q?y/Rs1JHeBKdZl5TDs0FmMfPGQBq1ab0cHKGT1w1ERnf0xpdxmVncMaQ4dlSW?= =?us-ascii?Q?pCOLmtcPo+WD5ASS6GTqsyeIT/XpUVNot0tDxM727GAOQ7seTugQM3djwLaG?= =?us-ascii?Q?5Lpsag2eCchYwQGI+7k5QRdLxJ5plxY4xEVYZ7Rgb7AZUbT7KonBrZLxuD7E?= =?us-ascii?Q?9cKmpFwl8MwT8X13Hx+SH1DRhJv8aQ7A6Oops+q+3PTS2y+vqD9CUsgnK32D?= =?us-ascii?Q?+KeHH4FgRQpUXBahOwE5xp85qJmc7S7/DOdJ0rAZSQEjrfJ9r2AfT1gRRRZY?= =?us-ascii?Q?egEDv3biwlW7XjHC2EMjwR/cEoe/+bqOgLryZbxqwiV8MXaJHERNa/ihhUXK?= =?us-ascii?Q?qchGv1kq0RBKW8vA4fsnoLovW2urkQamxVy1Negp+v7xmutEPHBc1a6CZouP?= =?us-ascii?Q?qnGZHTz1GxMP0gmEHrNvYjsdGFqyP/P9ZJzibs/x4RYRgBwJ+ZvLPS5Kjz1t?= =?us-ascii?Q?bnbat/62MPbCUCM2xYM/s4AAfMVsmvBRQpOCF9Cox2gHF7CEvMfRRtNDYIUQ?= =?us-ascii?Q?yIV/aBrPtoAdaazJ435YVDSwT/ttWoig/bKY7BniVg7R8fuam4bqRtAA3v+N?= =?us-ascii?Q?r9DUFfl1bLbixJ+NcmuB21NfTuDgKuY0dJ08SfmbuzpUEbkvYKLLevH9OgV1?= =?us-ascii?Q?sdsKKbKK9u766zyoU9HPWIeW?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 40a7f55c-510e-4ae7-2d47-08d9165ed6bc X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3834.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 May 2021 22:31:23.8257 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KDDkdqIuWnhXL/eIKb7Vgvqt+RdBXmlBJeVehuDj0RBYJjZp7/Jx1zBedeS28GsX X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4499 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 13, 2021 at 01:22:51PM -0700, Jacob Pan wrote: > Hi Tony, > > On Thu, 13 May 2021 12:57:49 -0700, "Luck, Tony" > wrote: > > > On Thu, May 13, 2021 at 12:46:21PM -0700, Jacob Pan wrote: > > > It seems there are two options: > > > 1. Add a new IOMMU API to set up a system PASID with a *separate* IOMMU > > > page table/domain, mark the device is PASID only with a flag. Use DMA > > > APIs to explicit map/unmap. Based on this PASID-only flag, Vendor IOMMU > > > driver will decide whether to use system PASID domain during map/unmap. > > > Not clear if we also need to make IOVA==kernel VA. > > > > > > 2. Add a new IOMMU API to setup a system PASID which points to > > > init_mm.pgd. This API only allows trusted device to bind with the > > > system PASID at its own risk. There is no need for DMA API. This is the > > > same as the current code except with an explicit API. > > > > > > Which option? > > > > Option #1 looks cleaner to me. Option #2 gives access to bits > > of memory that the users of system PASID shouldn't ever need > > to touch ... just map regions of memory that the kernel has > > a "struct page" for. > > > > What does "use DMA APIs to explicitly map/unmap" mean? Is that > > for the whole region? > > > If we map the entire kernel direct map during system PASID setup, then we > don't need to use DMA API to map/unmap certain range. > > I was thinking this system PASID page table could be on-demand. The mapping > is built by explicit use of DMA map/unmap APIs. Option 1 should be the PASID works exactly like a normal RID and uses all the normal DMA APIs and IOMMU mechanisms, whatever the platform implements. This might mean an iommu update on every operation or not. > > I'm expecting that once this system PASID has been initialized, > > then any accelerator device with a kernel use case would use the > > same PASID. I.e. DSA for page clearing, IAX for ZSwap compression > > & decompression, etc. > > > OK, sounds like we have to map the entire kernel VA with struct page as you > said. So we still by-pass DMA APIs, can we all agree on that? Option 2 should be the faster option, but not available in all cases. Option 1 isn't optional. DMA and IOMMU code has to be portable and this is the portable API. If you want to do option 1 and option 2 then give it a go, but in most common cases with the IOMMU in a direct map you shouldn't get a notable performance win. Jason