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[23.128.96.18]) by mx.google.com with ESMTP id c22si7493554edw.594.2021.05.17.03.22.09; Mon, 17 May 2021 03:22:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YW8aguL1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236378AbhEQKTe (ORCPT + 99 others); Mon, 17 May 2021 06:19:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236379AbhEQKTd (ORCPT ); Mon, 17 May 2021 06:19:33 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10680C061573 for ; Mon, 17 May 2021 03:18:17 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id m11so7990052lfg.3 for ; Mon, 17 May 2021 03:18:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=QpD2zMBxw5znlPKt4SJEqzKdA2fPgb5vzD+kazPbf2Q=; b=YW8aguL1Or6+vxZUZkBLdiM0tAjt2lRGVb2q7Un8iQZCfMuLZ2s8l9onWyOmLEsvC2 RwXXtW47esnkr/mlxu3DOWSA42AjLpTbAnm03enYxdFOJS30ZdBaRz4V3m5kqPh8wO+e bP6ouEwKpEOmN5KZ91tONBJCRfXitJt2PPXzLmPLcik0JewIp1qw2qP+SKdC/g+1iYSX tjA1aSLFOg1/7qFlAqANS4ZDVVaJu4fdn+U+eSYObQSbNxoMo27nxIOS1x8AlhvfqQjR 4uDfcuUAbBvrIjjFa3/5nmwLwPi3KHmFYu4J6V+HcwT9C6d3e6N3vQIpUCmDPtW07MEZ dmJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=QpD2zMBxw5znlPKt4SJEqzKdA2fPgb5vzD+kazPbf2Q=; b=K0Napnw0wxdNebFbqP35YcZohbofacDZh7+bXKtLibn/p6nfcMJ+M0GHgHV2IOOnjS w4NfG0ORzoxGAhHjNPPhU9zzYn5AMiJPow9TDvQQW6r9CCF8Qloau8U0AVVKTSMMepUT T5+JxZGJ/OAsPSguHQUUxIXbCgex5YZwA4MZrMD15RmSn7RwqvgU6Ad27FeKZ2hYODZT Wl1pGg4aN4GWB58BcDv2FAb1yjP2SPxLlKP56mNhSw44K+X6XgZQ1cphX61DbyoUz3kW VVeR8niZif3PVEw2ZN0xRLrQnNXPWQrSLYNm6ABc0lxx2EUhj4DLlj3q4rUN7o83ymEw s+5Q== X-Gm-Message-State: AOAM530kB0Dl/Rxd0rfLYGFu3q1pi4grwO6i5NF42rLmcdiXgklD6cJi gs88VvZKBJcwLrqOvj9dipSeCc4J9qi2OSiGoqgMRA== X-Received: by 2002:a05:6512:11ea:: with SMTP id p10mr89321lfs.157.1621246695068; Mon, 17 May 2021 03:18:15 -0700 (PDT) MIME-Version: 1.0 References: <20210512081211.200025-1-arnd@kernel.org> In-Reply-To: <20210512081211.200025-1-arnd@kernel.org> From: Linus Walleij Date: Mon, 17 May 2021 12:18:04 +0200 Message-ID: Subject: Re: [PATCH] ARM: fix gcc-10 thumb2-kernel regression To: Arnd Bergmann Cc: Russell King , Arnd Bergmann , stable , Daniel Thompson , Marek Vasut , Nathan Chancellor , Nick Desaulniers , Ard Biesheuvel , Nicolas Pitre , Geert Uytterhoeven , Mike Rapoport , Linux ARM , linux-kernel , clang-built-linux Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 12, 2021 at 10:13 AM Arnd Bergmann wrote: > From: Arnd Bergmann > > When building the kernel wtih gcc-10 or higher using the > CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y flag, the compiler picks a slightly > different set of registers for the inline assembly in cpu_init() that > subsequently results in a corrupt kernel stack as well as remaining in > FIQ mode. If a banked register is used for the last argument, the wrong > version of that register gets loaded into CPSR_c. When building in Arm > mode, the arguments are passed as immediate values and the bug cannot > happen. > > This got introduced when Daniel reworked the FIQ handling and was > technically always broken, but happened to work with both clang and gcc > before gcc-10 as long as they picked one of the lower registers. > This is probably an indication that still very few people build the > kernel in Thumb2 mode. > > Marek pointed out the problem on IRC, Arnd narrowed it down to this > inline assembly and Russell pinpointed the exact bug. > > Change the constraints to force the final mode switch to use a non-banked > register for the argument to ensure that the correct constant gets loaded. > Another alternative would be to always use registers for the constant > arguments to avoid the #ifdef that has now become more complex. > > Cc: # v3.18+ > Cc: Daniel Thompson > Reported-by: Marek Vasut > Fixes: c0e7f7ee717e ("ARM: 8150/3: fiq: Replace default FIQ handler") > Signed-off-by: Arnd Bergmann Wow. Nice bug hunt here, hats off! Reviewed-by: Linus Walleij Yours, Linus Walleij