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Date:   Mon, 17 May 2021 16:37:06 +0200
From:   Daniel Vetter <daniel@ffwll.ch>
To:     Paul Cercueil <paul@crapouillou.net>
Cc:     Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>,
        Sam Ravnborg <sam@ravnborg.org>, od@zcrc.me,
        linux-mips@vger.kernel.org, dri-devel@lists.freedesktop.org,
        linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH] drm/ingenic: Fix pixclock rate for 24-bit serial panels
Message-ID: <YKJ/ko7+HZix4znQ@phenom.ffwll.local>
Mail-Followup-To: Paul Cercueil <paul@crapouillou.net>,
        David Airlie <airlied@linux.ie>, Sam Ravnborg <sam@ravnborg.org>,
        od@zcrc.me, linux-mips@vger.kernel.org,
        dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
        stable@vger.kernel.org
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On Mon, May 17, 2021 at 03:30:45PM +0100, Paul Cercueil wrote:
> Hi Daniel,
> 
> Le lun., mai 17 2021 at 15:15:59 +0200, Daniel Vetter <daniel@ffwll.ch> a
> ?crit :
> > On Thu, May 13, 2021 at 01:29:30PM +0100, Paul Cercueil wrote:
> > >  Hi,
> > > 
> > >  Almost two months later,
> > 
> > Since you're committer it's expected that you go actively out to look
> > for
> > review or trade with someone else who has some patches that need a quick
> > look. It will not happen automatically, this is on you.
> 
> I maintain all drivers, platform code and DTS for Ingenic SoCs so I do my
> part, just not in this subsystem.
> 
> > Also generally after 2 weeks the patch is lost and you need to ping it.
> 
> OK. Then I guess I'll just include this one in a future patchset.

Well you do have an ack now. I just meant to highlight that generally it
doesn't happen automatically, and also that after 2 weeks generally a
patchset wont get attention anymore.
-Daniel

> 

> > -Daniel
> 
> Cheers,
> -Paul
> 
> > > 
> > > 
> > >  Le mar., mars 23 2021 at 14:40:08 +0000, Paul Cercueil
> > >  <paul@crapouillou.net> a ?crit :
> > >  > When using a 24-bit panel on a 8-bit serial bus, the pixel clock
> > >  > requested by the panel has to be multiplied by 3, since the
> > > subpixels
> > >  > are shifted sequentially.
> > >  >
> > >  > The code (in ingenic_drm_encoder_atomic_check) already computed
> > >  > crtc_state->adjusted_mode->crtc_clock accordingly, but
> > > clk_set_rate()
> > >  > used crtc_state->adjusted_mode->clock instead.
> > >  >
> > >  > Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when
> > > using a
> > >  > 3x8-bit panel")
> > >  > Cc: stable@vger.kernel.org # v5.10
> > >  > Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> > > 
> > >  Can I get an ACK for my patch?
> > > 
> > >  Thanks!
> > >  -Paul
> > > 
> > >  > ---
> > >  >  drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +-
> > >  >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >  >
> > >  > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
> > >  > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
> > >  > index d60e1eefc9d1..cba68bf52ec5 100644
> > >  > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
> > >  > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
> > >  > @@ -342,7 +342,7 @@ static void
> > > ingenic_drm_crtc_atomic_flush(struct
> > >  > drm_crtc *crtc,
> > >  >  	if (priv->update_clk_rate) {
> > >  >  		mutex_lock(&priv->clk_mutex);
> > >  >  		clk_set_rate(priv->pix_clk,
> > >  > -			     crtc_state->adjusted_mode.clock * 1000);
> > >  > +			     crtc_state->adjusted_mode.crtc_clock * 1000);
> > >  >  		priv->update_clk_rate = false;
> > >  >  		mutex_unlock(&priv->clk_mutex);
> > >  >  	}
> > >  > --
> > >  > 2.30.2
> > >  >
> > > 
> > > 
> > 
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> 
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch