Received: by 2002:a05:6520:4211:b029:f4:110d:56bc with SMTP id o17csp731994lkv; Tue, 18 May 2021 18:35:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwlmIy5+DOXuHvlvKkDNCji9tYIn0tMvZ6CSKhfzLpuTzaUnTZ2LDilaBasvbHnxn8pUXlw X-Received: by 2002:a05:6e02:1aa9:: with SMTP id l9mr7719033ilv.24.1621388114008; Tue, 18 May 2021 18:35:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621388114; cv=none; d=google.com; s=arc-20160816; b=vs8Ouq7GxveMDypbBJ1gjgsx8qbwZsdsDM8qZY2MFvtv8AMFPrUG6d/u8tPb3hDwTr MtiM4E30ozSEujNKZTQUbhymZkmvFdZUcuH6p9qk9PWWNDwQkvmSLyGKQm/nzQFnOvHA IL8baLWr6IBl/Xqlrpj6zqjCg8vD1RBRxqsJXn72zjfCgagBlEsSN54FzZVzrGyeuWb9 qxg8C3lVigPDLmIt9QbYrTlj73RovfhPDFuYhdxAB98z+G1uYTjFORzkpTjBDo1KdsgO RsWihIsOfe3FBd8GEgUcauiCoGD9N3pgaiyHD8Qnvd1Ss0sg3Bxuav06AkGYmiBaTcAq PeLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UYjdfSw7ndqIS5WR6CeYrp/D/E+mLdRADgJD7MCncgI=; b=cEBqKi2/ErwHs6dlk83hb8M6s138mGRCmWCg+T6j+83IhYiDMisXf6hXnN/Jwh2Tvk kUZ459y0lRk7tfvQDUf1xeRxVwPymbuV+qJFSzVrQ/2+m2we3RPdMkAUjEgP38SUMrx/ svnQk4lBt/tKsnQIU0ZsG2M3lcharTZ0A0lCK+/mL0vURj5D/KtrkRhoVZzxJOiBnhvo r85JIxTBZCUlzYlIMveQuLTs1O+XoK2fDx8EWz8JRUarM/TWZFruG1qOHSk+r/BdPYi6 U0Er9TUU5dAh7sgaYAUv62k3a3gwRS94zAM40Cc+X+y42ktCvjdoh5q+SufhdMKNnxLj G5Ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@svanheule.net header.s=mail1707 header.b=VPhcRk1C; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=svanheule.net Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k2si21793683ils.162.2021.05.18.18.35.01; Tue, 18 May 2021 18:35:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@svanheule.net header.s=mail1707 header.b=VPhcRk1C; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=svanheule.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234181AbhEQTaK (ORCPT + 99 others); Mon, 17 May 2021 15:30:10 -0400 Received: from polaris.svanheule.net ([84.16.241.116]:57460 "EHLO polaris.svanheule.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233897AbhEQTaA (ORCPT ); Mon, 17 May 2021 15:30:00 -0400 Received: from terra.local.svanheule.net (unknown [IPv6:2a02:a03f:eafb:ee01:404a:340a:91cb:c07b]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id ABA421FFBFA; Mon, 17 May 2021 21:28:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1621279723; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UYjdfSw7ndqIS5WR6CeYrp/D/E+mLdRADgJD7MCncgI=; b=VPhcRk1CYZmz7Wq/HHkBPB8LqTwCAl+VwiSsivuOJ7G4ve5jDcE4pU1aWrp3o0ylfFrMJe aoj+5WmzQarhxUdnqLzOoaNGVqtUoanBTRRTyOXLeK3agXdeGve/aO6VoSWOVW5DQkMSki vopxVm3SFuCbU31T1LTkn9wekp3DsTf2oWyXIqz0Aq1Ve2IFYZjNF1GRiShxjBI6SbBH/7 Z3BH9AUaNwCnKUvkgocVFfB/MjDucgWSBMFXWUx4smeXRNxx9SgnQGf+Q9edcOf5VGjyGC pRjZIi3IG4hITPxPcFJsRMokoBNpOPv3liPTfTtEoOk1AExCzmyUe3sEBeMDUA== From: Sander Vanheule To: Pavel Machek , Rob Herring , Lee Jones , Mark Brown , Greg Kroah-Hartman , "Rafael J . Wysocki" , Michael Walle , Linus Walleij , Bartosz Golaszewski , linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Andrew Lunn , Andy Shevchenko , linux-kernel@vger.kernel.org, Sander Vanheule Subject: [PATCH v2 4/7] dt-bindings: mfd: Binding for RTL8231 Date: Mon, 17 May 2021 21:28:06 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a binding description for the Realtek RTL8231, a GPIO and LED expander chip commonly used in ethernet switches based on a Realtek switch SoC. These chips can be addressed via an MDIO or SMI bus, or used as a plain 36-bit shift register. This binding only describes the feature set provided by the MDIO/SMI configuration, and covers the GPIO, PWM, and pin control properties. The LED properties are defined in a separate binding. Signed-off-by: Sander Vanheule --- .../bindings/mfd/realtek,rtl8231.yaml | 202 ++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/realtek,rtl8231.yaml diff --git a/Documentation/devicetree/bindings/mfd/realtek,rtl8231.yaml b/Documentation/devicetree/bindings/mfd/realtek,rtl8231.yaml new file mode 100644 index 000000000000..24ab7344c0c4 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/realtek,rtl8231.yaml @@ -0,0 +1,202 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/realtek,rtl8231.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL8231 GPIO and LED expander. + +maintainers: + - Sander Vanheule + +description: | + The RTL8231 is a GPIO and LED expander chip, providing up to 37 GPIOs, up to + 88 LEDs, and up to one PWM output. This device is frequently used alongside + Realtek switch SoCs, to provide additional I/O capabilities. + + To manage the RTL8231's features, its strapping pins can be used to configure + it in one of three modes: shift register, MDIO device, or SMI device. The + shift register mode does not need special support. In MDIO or SMI mode, most + pins can be configured as a GPIO output, LED matrix scan line/column, or as a + PWM output. + + The GPIO and pin control are part of the main node. PWM and LED support are + configured as sub-nodes. + +properties: + compatible: + const: realtek,rtl8231 + + reg: + description: MDIO or SMI device address. + maxItems: 1 + + # GPIO support + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + The first cell is the pin number and the second cell is used to specify + the gpio active state. + + gpio-ranges: + description: | + Must reference itself, and provide a zero-based mapping for 37 pins. + maxItems: 1 + + # Pin muxing and configuration + realtek,drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Common drive strength used for all GPIO output pins, must be 4mA or 8mA. + On reset, this value will default to 8mA. + enum: [4, 8] + + # LED scanning matrix + leds: + $ref: ../leds/realtek,rtl8231-leds.yaml# + + # PWM output + pwm: + type: object + description: | + Subnode describing the PWM peripheral. To use the PWM output, gpio35 must + be muxed to its 'pwm' function. Valid frequency values for consumers are + 1200, 1600, 2000, 2400, 2800, 3200, 4000, and 4800. + + properties: + "#pwm-cells": + description: | + Twos cells with PWM index (must be 0) and PWM frequency in Hz. + const: 2 + + required: + - "#pwm-cells" + +patternProperties: + "-pins$": + type: object + $ref: ../pinctrl/pinmux-node.yaml# + + properties: + pins: + items: + oneOf: + - enum: ["gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36"] + minItems: 1 + maxItems: 37 + function: + description: | + Select which function to use. "gpio" is supported for all pins, "led" is supported + for pins 0-34, "pwm" is supported for pin 35. + enum: ["gpio", "led", "pwm"] + + required: + - pins + - function + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - gpio-ranges + +additionalProperties: false + +examples: + - | + // Minimal example + mdio { + #address-cells = <1>; + #size-cells = <0>; + + expander0: expander@0 { + compatible = "realtek,rtl8231"; + reg = <0>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&expander0 0 0 37>; + }; + }; + - | + // All bells and whistles included + #include + mdio { + #address-cells = <1>; + #size-cells = <0>; + + expander1: expander@1 { + compatible = "realtek,rtl8231"; + reg = <1>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&expander1 0 0 37>; + + realtek,drive-strength = <4>; + + button-pins { + pins = "gpio36"; + function = "gpio"; + input-debounce = "100000"; + }; + + pwm-pins { + pins = "gpio35"; + function = "pwm"; + }; + + led-pins { + pins = "gpio0", "gpio1", "gpio3", "gpio4"; + function = "led"; + }; + + pwm { + #pwm-cells = <2>; + }; + + leds { + compatible = "realtek,rtl8231-leds"; + #address-cells = <2>; + #size-cells = <0>; + + realtek,led-scan-mode = "single-color"; + + led@0,0 { + reg = <0 0>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + }; + + led@0,1 { + reg = <0 1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + }; + + led@1,0 { + reg = <1 0>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + }; + + led@1,1 { + reg = <1 1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + }; + }; + }; + }; -- 2.31.1