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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id e10sm18928907wrw.20.2021.05.17.12.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 12:32:20 -0700 (PDT) From: Corentin Labbe To: arnd@arndb.de, linus.walleij@linaro.org, olof@lixom.net, robh+dt@kernel.org, soc@kernel.org, ulli.kroll@googlemail.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH 5/5] ARM: gemini: add device tree for ssi1328 Date: Mon, 17 May 2021 19:32:05 +0000 Message-Id: <20210517193205.691147-6-clabbe@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210517193205.691147-1-clabbe@baylibre.com> References: <20210517193205.691147-1-clabbe@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The SSI 1328 is a NAS box running a SL3516 SoC. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/gemini-ssi1328.dts | 162 +++++++++++++++++++++++++++ 2 files changed, 163 insertions(+) create mode 100644 arch/arm/boot/dts/gemini-ssi1328.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bb30d13c9c60..0a9f6001b90b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -220,6 +220,7 @@ dtb-$(CONFIG_ARCH_GEMINI) += \ gemini-rut1xx.dtb \ gemini-sl93512r.dtb \ gemini-sq201.dtb \ + gemini-ssi1328.dtb \ gemini-wbd111.dtb \ gemini-wbd222.dtb dtb-$(CONFIG_ARCH_HI3xxx) += \ diff --git a/arch/arm/boot/dts/gemini-ssi1328.dts b/arch/arm/boot/dts/gemini-ssi1328.dts new file mode 100644 index 000000000000..1112007c9d6f --- /dev/null +++ b/arch/arm/boot/dts/gemini-ssi1328.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Corentin Labbe + * Device Tree file for SSI 1328 + */ + +/dts-v1/; + +#include "gemini.dtsi" + +/ { + model = "SSI 1328"; + compatible = "ssi,1328", "cortina,gemini"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; + + chosen { + bootargs = "console=ttyS0,19200n8 initrd=0x800000,9M"; + stdout-path = &uart0; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ + <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + /* LAN Marvell 88E1118 */ + phy0: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + /* We lack the knowledge of necessary GPIO to achieve + * Gigabit + */ + max-speed = <100>; + }; + /* WAN ICPlus IP101A */ + phy1: ethernet-phy@2 { + reg = <2>; + device_type = "ethernet-phy"; + }; + }; +}; + +ðernet { + status = "okay"; + ethernet-port@0 { + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet-port@1 { + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; +}; + +&flash { + status = "okay"; + /* 32MB of flash */ + reg = <0x30000000 0x03200000>; + #address-cells = <1>; + #size-cells = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "RedBoot"; + reg = <0x00000000 0x00020000>; + read-only; + }; + partition@20000 { + label = "Kernel"; + reg = <0x00020000 0x00300000>; + }; + partition@320000 { + label = "Ramdisk"; + reg = <0x00320000 0x00600000>; + }; + partition@920000 { + label = "Application"; + reg = <0x00920000 0x00600000>; + }; + partition@f20000 { + label = "VCTL"; + reg = <0x00f20000 0x00020000>; + read-only; + }; + partition@f40000 { + label = "CurConf"; + reg = <0x00f40000 0x000a0000>; + read-only; + }; + partition@fe0000 { + label = "FIS directory"; + reg = <0x00fe0000 0x00200000>; + read-only; + }; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_default_pins>; +}; + +&ide0 { + status = "okay"; +}; + +&ide1 { + status = "okay"; +}; + +&sata { + cortina,gemini-ata-muxmode = <0>; + cortina,gemini-enable-sata-bridge; + status = "okay"; +}; + +&syscon { + pinctrl { + /* + * gpio0agrp cover line 0-4 + * gpio0bgrp cover line 5 + */ + gpio0_default_pins: pinctrl-gpio0 { + mux { + function = "gpio0"; + groups = "gpio0agrp", "gpio0bgrp"; + }; + }; + pinctrl-gmii { + /* This platform use both the ethernet ports */ + mux { + function = "gmii"; + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; + }; + }; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; -- 2.26.3