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References: <20210517171205.1581938-1-abelvesa@kernel.org> <20210517171205.1581938-6-abelvesa@kernel.org>
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From:   Dong Aisheng <dongas86@gmail.com>
Date:   Tue, 18 May 2021 15:54:25 +0800
Message-ID: <CAA+hA=RNfWYaE81yYv5Dyt8QSXd_NTGcwjWwitiRNe4ZOtRWvw@mail.gmail.com>
Subject: Re: [PATCH 5/7] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
To:     Abel Vesa <abelvesa@kernel.org>
Cc:     Rob Herring <robh@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        Jacky Bai <ping.bai@nxp.com>,
        Dong Aisheng <aisheng.dong@nxp.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        devicetree <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        Abel Vesa <abel.vesa@nxp.com>
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On Tue, May 18, 2021 at 1:16 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> Add the ddr subsys dtsi for i.MX8DXL. Additional db pmu is added
> compared to i.MX8QXP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi    | 34 +++++++++++++++++++
>  1 file changed, 34 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
> new file mode 100644
> index 000000000000..640b43f5ae97
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +&ddr_subsys {
> +       db_ipg_clk: clock-db-ipg {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <456000000>;
> +               clock-output-names = "db_ipg_clk";
> +       };
> +
> +       db_pmu0: db-pmu@5ca40000 {
> +               compatible = "fsl,imx8dxl-db-pmu";
> +               reg = <0x5ca40000 0x10000>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
> +               clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>;

fix lpcg index

> +               clock-names = "ipg", "cnt";
> +               power-domains = <&pd IMX_SC_R_PERF>;
> +       };
> +
> +       db_pmu0_lpcg: clock-controller@5cae0000 {
> +               compatible = "fsl,imx8qxp-lpcg";
> +               reg = <0x5cae0000 0x10000>;
> +               #clock-cells = <1>;
> +               clocks = <&db_ipg_clk>, <&db_ipg_clk>;
> +               bit-offset = <0 16>;

fix lpcg index by using macro

> +               clock-output-names = "perf_lpcg_cnt_clk",
> +                                    "perf_lpcg_ipg_clk";
> +               power-domains = <&pd IMX_SC_R_PERF>;
> +       };
> +};
> --
> 2.31.1
>
>
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