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Date:   Wed, 19 May 2021 15:24:37 -0700
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Subject: Re: [PATCH v3 1/8] x86/traps: add X86_NR_HW_TRAPS to <asm/trapnr.h>
To:     Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>,
        Andy Lutomirski <luto@kernel.org>,
        Borislav Petkov <bp@alien8.de>
CC:     Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
From:   "H. Peter Anvin" <hpa@zytor.com>
Message-ID: <E1F71F76-747B-4A22-98A2-5FBF17B83A1A@zytor.com>
Precedence: bulk

It is not right now, but it will be used in the FRED enabling patchset at t=
he very least (since the number of exception vectors and FIRST_EXTERNAL_VEC=
TOR are not necessarily the same anymore=2E)

On May 19, 2021 3:17:57 PM PDT, Thomas Gleixner <tglx@linutronix=2Ede> wro=
te:
>On Wed, May 19 2021 at 14:21, H=2E Peter Anvin wrote:
>> From: "H=2E Peter Anvin (Intel)" <hpa@zytor=2Ecom>
>>
>> The x86 architecture supports up to 32 trap vectors=2E Add that
>constant
>> to <asm/trapnr=2Eh>=2E
>
>Where is that actually used?
>
>Thanks,
>
>        tglx

--=20
Sent from my Android device with K-9 Mail=2E Please excuse my brevity=2E