Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp2117329pxj; Thu, 20 May 2021 00:03:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzSd8wWpFCaV0T2NSoB2ObqJONmYJ5KxWwVlDN7d4P64vhswgT9zPbjc1TcgTN8d5ibIvep X-Received: by 2002:aa7:d659:: with SMTP id v25mr3382751edr.271.1621494215376; Thu, 20 May 2021 00:03:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621494215; cv=none; d=google.com; s=arc-20160816; b=LzGXZEYPCzjgCKR4USqYOeTsywXEzxz0OSd7Ttj34ytOzmK9hbq94l6km1AOimI/FK yZjvSh/GG45i/atFwhjl5wUyjkhEQNYuOLNWi2nguC3IRuSbGws+7feNXPK1ks0fJAES HIlU+B4kY5ZUVtwWjA1OmAQqpu66BK766pQCDEjd6/gWnNam6j1E6XmAqa7HsDETkaAo JBd/CXx5p0TcZ0u27xaepyh99YijdsPTXYEs/fdXx94SKD6zYAXUc9eIZx/56G4545U9 R6dCrcxrG2e3BcSDnXVug7WgGKBOzkJ6GzFaluK+diXACUM7L8KxD1GrqFXmKpiS4BCg 1T/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:ironport-sdr:ironport-sdr; bh=EHJqCMJB8Y+IFTrzTOC3UDbqnLOMJ7ZYOuH3GFqvM54=; b=CrbrM7Wo+mRYvfKSqmcIaXnHh3VVTrZma+kKstiwsEdF++XiQFVYNvgKGMFOMOjFi1 3OrMWosLSsEjIJiITKlLjasgp54IiUsyRMnludi45wWy7a1dg9DZwGtwSQGHeb2lokiB iz+QSdXBzAt/1vMO14Dwh3GqmXOU9uD/jUKON5+zidvyFRDtUTglZLAF4lmBNeWHUIVK h8QQBVudldqzVSRKSEJIqroVvcJGSL0sKGa65qmx/EwScfBV2V7m0VdMqFGPFsqEZ9Eh 3lDH+SVR+nFzTzcUQZqjqm0Pg1kLKDfHTH3qxpIx7l3qqGMEu4+wS9c47RqEhy6gdZms kvqQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h10si1456464edv.387.2021.05.20.00.03.04; Thu, 20 May 2021 00:03:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230429AbhETHDa (ORCPT + 99 others); Thu, 20 May 2021 03:03:30 -0400 Received: from mga05.intel.com ([192.55.52.43]:53040 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230355AbhETHD1 (ORCPT ); Thu, 20 May 2021 03:03:27 -0400 IronPort-SDR: O1N4ph2+ZzBG6NfPowqs0ASPQxp3gbLrXZk6nOfH8k8jBAsbLNR2dyVcaO57WG8jSwgPan+MFb iL1pFXfd2eFA== X-IronPort-AV: E=McAfee;i="6200,9189,9989"; a="286691041" X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="286691041" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2021 00:02:07 -0700 IronPort-SDR: D+Ndb5GCuNesXQ7WQcCd/fFCQGWxG8CuExXtgLs33BVwxvmMGeNsH2OX7rAbw8Ljo2r4zkkgWG lsLjP2naZbHg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="543206797" Received: from kbl-ppc.sh.intel.com ([10.239.159.163]) by fmsmga001.fm.intel.com with ESMTP; 20 May 2021 00:02:04 -0700 From: Jin Yao To: acme@kernel.org, jolsa@kernel.org, peterz@infradead.org, mingo@redhat.com, alexander.shishkin@linux.intel.com Cc: Linux-kernel@vger.kernel.org, ak@linux.intel.com, kan.liang@intel.com, yao.jin@intel.com, Jin Yao Subject: [PATCH v1 1/5] perf util: Check mem-loads auxiliary event Date: Thu, 20 May 2021 15:00:36 +0800 Message-Id: <20210520070040.710-2-yao.jin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210520070040.710-1-yao.jin@linux.intel.com> References: <20210520070040.710-1-yao.jin@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For some platforms, an auxiliary event has to be enabled simultaneously with the load latency event. For Alderlake, the auxiliary event is created in "cpu_core" pmu. So first we need to check the existing of "cpu_core" pmu and then check if this pmu has auxiliary event. Signed-off-by: Jin Yao --- tools/perf/arch/x86/util/mem-events.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tools/perf/arch/x86/util/mem-events.c b/tools/perf/arch/x86/util/mem-events.c index 588110fd8904..e79232e3f2a0 100644 --- a/tools/perf/arch/x86/util/mem-events.c +++ b/tools/perf/arch/x86/util/mem-events.c @@ -11,8 +11,13 @@ static bool mem_loads_name__init; bool is_mem_loads_aux_event(struct evsel *leader) { - if (!pmu_have_event("cpu", "mem-loads-aux")) - return false; + if (perf_pmu__find("cpu")) { + if (!pmu_have_event("cpu", "mem-loads-aux")) + return false; + } else if (perf_pmu__find("cpu_core")) { + if (!pmu_have_event("cpu_core", "mem-loads-aux")) + return false; + } return leader->core.attr.config == MEM_LOADS_AUX; } -- 2.17.1