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h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=APthq424sGAGaRBs3OCr9n7FGV+NylmYmvNzYhKlHLQ=; b=e0UMTicUoNhnmD9chzeACx87aUfDsQsUtUGl5QXIugTWnNUHI4m5hdZZLsEhrpkZVf /xq/64B8NU9SuA2YWI/KHLDJLW43cHyS2cxAUuZ9pk6dyPVyTZ9zC50b+JOXzYqgUb17 KvAhyOc08lXfj5PgLsZDYsfzfkIqjSsoIa1taZz5d6c8CTJMx8E/e+X7gXuRb65GS30y 9Rq0Kp41tGO3FO6iXDETzH0Rb7UxAgNu4GbgpK2FY8u5yNrz3Kej+MFDb3l47KHWKJgo seHM6UZAM9WOdhwGX+TcGD5SyOPlbce3wxisXOYo9m2qxm8VhktMv9iZSyEjBGeWlvu0 Rb5g== X-Gm-Message-State: AOAM532IS3aVnu/XLxBexQRamxQq2Kyt5SNFZ/X+TdYa9+7mFpe99v5A R3j64bVFmi37d3uACinMCWzecdc5w9gbC7NWubUlY+6SMN++n+SS X-Received: by 2002:adf:db4e:: with SMTP id f14mr5056236wrj.48.1621527223547; Thu, 20 May 2021 09:13:43 -0700 (PDT) MIME-Version: 1.0 References: <20210510012438.6293-1-yao.jin@linux.intel.com> <20210510012438.6293-3-yao.jin@linux.intel.com> In-Reply-To: <20210510012438.6293-3-yao.jin@linux.intel.com> From: Ian Rogers Date: Thu, 20 May 2021 09:13:29 -0700 Message-ID: Subject: Re: [PATCH 2/4] perf vendor events: Add uncore event list for Icelake Server To: Jin Yao Cc: Arnaldo Carvalho de Melo , Jiri Olsa , Peter Zijlstra , Ingo Molnar , Alexander Shishkin , LKML , Andi Kleen , Kan Liang , "Jin, Yao" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, May 9, 2021 at 6:28 PM Jin Yao wrote: > > Add JSON uncore events for Icelake Server to perf. > > Based on JSON list v1.04 > https://download.01.org/perfmon/ICX/ Acked-by: Ian Rogers Could perf-uncore-events-icx.csv be added to: https://github.com/intel/event-converter-for-linux-perf Thanks, Ian > Signed-off-by: Jin Yao > Reviewed-by: Andi Kleen > --- > .../arch/x86/icelakex/uncore-memory.json | 333 +++ > .../arch/x86/icelakex/uncore-other.json | 2476 +++++++++++++++++ > .../arch/x86/icelakex/uncore-power.json | 10 + > 3 files changed, 2819 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json > create mode 100644 tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json > create mode 100644 tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json > > diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json > new file mode 100644 > index 000000000000..5f0d2c462940 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json > @@ -0,0 +1,333 @@ > +[ > + { > + "BriefDescription": "2LM Tag Check : Hit in Near Memory Cache", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xD3", > + "EventName": "UNC_M_TAGCHK.HIT", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "2LM Tag Check : Miss, no data in this line", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xD3", > + "EventName": "UNC_M_TAGCHK.MISS_CLEAN", > + "PerPkg": "1", > + "UMask": "0x02", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "2LM Tag Check : Miss, existing data may be evicted to Far Memory", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xD3", > + "EventName": "UNC_M_TAGCHK.MISS_DIRTY", > + "PerPkg": "1", > + "UMask": "0x04", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "2LM Tag Check : Read Hit in Near Memory Cache", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xD3", > + "EventName": "UNC_M_TAGCHK.NM_RD_HIT", > + "PerPkg": "1", > + "UMask": "0x08", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "2LM Tag Check : Write Hit in Near Memory Cache", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xD3", > + "EventName": "UNC_M_TAGCHK.NM_WR_HIT", > + "PerPkg": "1", > + "UMask": "0x10", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "DRAM Precharge commands. : Precharge due to read", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x02", > + "EventName": "UNC_M_PRE_COUNT.RD", > + "PerPkg": "1", > + "UMask": "0x04", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "DRAM Precharge commands. : Precharge due to write", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x02", > + "EventName": "UNC_M_PRE_COUNT.WR", > + "PerPkg": "1", > + "UMask": "0x08", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "All DRAM read CAS commands issued (including underfills)", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x04", > + "EventName": "UNC_M_CAS_COUNT.RD", > + "PerPkg": "1", > + "UMask": "0x0f", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "All DRAM write CAS commands issued", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x04", > + "EventName": "UNC_M_CAS_COUNT.WR", > + "PerPkg": "1", > + "UMask": "0x30", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "All DRAM CAS commands issued", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x04", > + "EventName": "UNC_M_CAS_COUNT.ALL", > + "PerPkg": "1", > + "UMask": "0x3f", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Number of DRAM Refreshes Issued", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x45", > + "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Number of DRAM Refreshes Issued", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x45", > + "EventName": "UNC_M_DRAM_REFRESH.PANIC", > + "PerPkg": "1", > + "UMask": "0x02", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Number of DRAM Refreshes Issued", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x45", > + "EventName": "UNC_M_DRAM_REFRESH.HIGH", > + "PerPkg": "1", > + "UMask": "0x04", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Read Pending Queue Allocations", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x10", > + "EventName": "UNC_M_RPQ_INSERTS.PCH0", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Read Pending Queue Allocations", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x10", > + "EventName": "UNC_M_RPQ_INSERTS.PCH1", > + "PerPkg": "1", > + "UMask": "0x02", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Write Pending Queue Allocations", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x20", > + "EventName": "UNC_M_WPQ_INSERTS.PCH0", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Write Pending Queue Allocations", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x20", > + "EventName": "UNC_M_WPQ_INSERTS.PCH1", > + "PerPkg": "1", > + "UMask": "0x02", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "DRAM Precharge commands. : Precharge due to page table", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x02", > + "EventName": "UNC_M_PRE_COUNT.PGT", > + "PerPkg": "1", > + "UMask": "0x10", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "DRAM Clockticks", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventName": "UNC_M_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Half clockticks for IMC", > + "Counter": "FIXED", > + "CounterType": "FIXED", > + "EventCode": "0xff", > + "EventName": "UNC_M_HCLOCKTICKS", > + "PerPkg": "1", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Read Pending Queue Occupancy", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x80", > + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", > + "PerPkg": "1", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Read Pending Queue Occupancy", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x81", > + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", > + "PerPkg": "1", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Write Pending Queue Occupancy", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x82", > + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", > + "PerPkg": "1", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "Write Pending Queue Occupancy", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", > + "PerPkg": "1", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "DRAM Activate Count : All Activates", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x01", > + "EventName": "UNC_M_ACT_COUNT.ALL", > + "PerPkg": "1", > + "UMask": "0x0B", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "DRAM Precharge commands", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x02", > + "EventName": "UNC_M_PRE_COUNT.ALL", > + "PerPkg": "1", > + "UMask": "0x1C", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "PMM Read Pending Queue Occupancy", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xE0", > + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "PMM Read Queue Inserts", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xE3", > + "EventName": "UNC_M_PMM_RPQ_INSERTS", > + "PerPkg": "1", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "PMM Write Queue Inserts", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xE7", > + "EventName": "UNC_M_PMM_WPQ_INSERTS", > + "PerPkg": "1", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "PMM Commands : All", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xEA", > + "EventName": "UNC_M_PMM_CMD1.ALL", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "PMM Commands : Reads - RPQ", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xEA", > + "EventName": "UNC_M_PMM_CMD1.RD", > + "PerPkg": "1", > + "UMask": "0x02", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "PMM Commands : Writes", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xEA", > + "EventName": "UNC_M_PMM_CMD1.WR", > + "PerPkg": "1", > + "UMask": "0x04", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "PMM Commands : Underfill reads", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xEA", > + "EventName": "UNC_M_PMM_CMD1.UFILL_RD", > + "PerPkg": "1", > + "UMask": "0x08", > + "Unit": "iMC" > + }, > + { > + "BriefDescription": "PMM Write Pending Queue Occupancy", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xE4", > + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "iMC" > + } > +] > diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json > new file mode 100644 > index 000000000000..52f2301582bb > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json > @@ -0,0 +1,2476 @@ > +[ > + { > + "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x50", > + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", > + "PerPkg": "1", > + "UMask": "0x10", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x50", > + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", > + "PerPkg": "1", > + "UMask": "0x20", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Local read requests that miss the SF/LLC and are sent to the CHA's home agent", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x50", > + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Remote read requests sent to the CHA's home agent", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x50", > + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", > + "PerPkg": "1", > + "UMask": "0x02", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Local write requests that miss the SF/LLC and are sent to the CHA's home agent", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x50", > + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", > + "PerPkg": "1", > + "UMask": "0x04", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Remote write requests sent to the CHA's home agent", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x50", > + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", > + "PerPkg": "1", > + "UMask": "0x08", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Clockticks of the uncore caching &amp; home agent (CHA)", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventName": "UNC_CHA_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x59", > + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x5B", > + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Lines Victimized : All Lines Victimized", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x37", > + "EventName": "UNC_CHA_LLC_VICTIMS.ALL", > + "PerPkg": "1", > + "UMask": "0x0F", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x50", > + "EventName": "UNC_CHA_REQUESTS.READS", > + "PerPkg": "1", > + "UMask": "0x03", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x50", > + "EventName": "UNC_CHA_REQUESTS.WRITES", > + "PerPkg": "1", > + "UMask": "0x0c", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Snoop filter capacity evictions for E-state entries", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x3D", > + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", > + "PerPkg": "1", > + "UMask": "0x02", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Snoop filter capacity evictions for M-state entries", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x3D", > + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Snoop filter capacity evictions for S-state entries", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x3D", > + "EventName": "UNC_CHA_SF_EVICTION.S_STATE", > + "PerPkg": "1", > + "UMask": "0x04", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : All requests from iA Cores", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA", > + "PerPkg": "1", > + "UMask": "0xC001FF01", > + "UMaskExt": "0xC001FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", > + "PerPkg": "1", > + "UMask": "0xC001FD01", > + "UMaskExt": "0xC001FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", > + "PerPkg": "1", > + "UMask": "0xC80FFD01", > + "UMaskExt": "0xC80FFD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", > + "PerPkg": "1", > + "UMask": "0xC817FD01", > + "UMaskExt": "0xC817FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", > + "PerPkg": "1", > + "UMask": "0xCCC7FD01", > + "UMaskExt": "0xCCC7FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", > + "PerPkg": "1", > + "UMask": "0xC807FD01", > + "UMaskExt": "0xC807FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", > + "PerPkg": "1", > + "UMask": "0xC001FE01", > + "UMaskExt": "0xC001FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", > + "PerPkg": "1", > + "UMask": "0xC80FFE01", > + "UMaskExt": "0xC80FFE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", > + "PerPkg": "1", > + "UMask": "0xC817FE01", > + "UMaskExt": "0xC817FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", > + "PerPkg": "1", > + "UMask": "0xCCC7FE01", > + "UMaskExt": "0xCCC7FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", > + "PerPkg": "1", > + "UMask": "0xC807FE01", > + "UMaskExt": "0xC807FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : All requests from IO Devices", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO", > + "PerPkg": "1", > + "UMask": "0xC001FF04", > + "UMaskExt": "0xC001FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", > + "PerPkg": "1", > + "UMask": "0xC001FD04", > + "UMaskExt": "0xC001FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", > + "PerPkg": "1", > + "UMask": "0xC001FE04", > + "UMaskExt": "0xC001FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : All requests from iA Cores", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", > + "PerPkg": "1", > + "UMask": "0xC001FF01", > + "UMaskExt": "0xC001FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", > + "PerPkg": "1", > + "UMask": "0xC001FD01", > + "UMaskExt": "0xC001FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", > + "PerPkg": "1", > + "UMask": "0xC001FE01", > + "UMaskExt": "0xC001FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", > + "PerPkg": "1", > + "UMask": "0xC80FFE01", > + "UMaskExt": "0xC80FFE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", > + "PerPkg": "1", > + "UMask": "0xC817FE01", > + "UMaskExt": "0xC817FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", > + "PerPkg": "1", > + "UMask": "0xC807FE01", > + "UMaskExt": "0xC807FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : All requests from IO Devices", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", > + "PerPkg": "1", > + "UMask": "0xC001FF04", > + "UMaskExt": "0xC001FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", > + "PerPkg": "1", > + "UMask": "0xC001FD04", > + "UMaskExt": "0xC001FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", > + "PerPkg": "1", > + "UMask": "0xC001FE04", > + "UMaskExt": "0xC001FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", > + "PerPkg": "1", > + "UMask": "0xCC43FE04", > + "UMaskExt": "0xCC43FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "CMS Clockticks", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc0", > + "EventName": "UNC_CHA_CMS_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", > + "PerPkg": "1", > + "UMask": "0xC88FFD01", > + "UMaskExt": "0xC88FFD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", > + "PerPkg": "1", > + "UMask": "0xC897FD01", > + "UMaskExt": "0xC897FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", > + "PerPkg": "1", > + "UMask": "0xC887FD01", > + "UMaskExt": "0xC887FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", > + "PerPkg": "1", > + "UMask": "0xC88FFE01", > + "UMaskExt": "0xC88FFE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", > + "PerPkg": "1", > + "UMask": "0xC897FE01", > + "UMaskExt": "0xC897FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", > + "PerPkg": "1", > + "UMask": "0xC887FE01", > + "UMaskExt": "0xC887FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", > + "PerPkg": "1", > + "UMask": "0xCC43FD04", > + "UMaskExt": "0xCC43FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", > + "PerPkg": "1", > + "UMask": "0xCC43FF04", > + "UMaskExt": "0xCC43FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", > + "PerPkg": "1", > + "UMask": "0xC887FF01", > + "UMaskExt": "0xC887FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", > + "PerPkg": "1", > + "UMask": "0xC807FF01", > + "UMaskExt": "0xC807FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", > + "PerPkg": "1", > + "UMask": "0xCCC7FF01", > + "UMaskExt": "0xCCC7FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", > + "PerPkg": "1", > + "UMask": "0xC897FF01", > + "UMaskExt": "0xC897FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", > + "PerPkg": "1", > + "UMask": "0xC80FFF01", > + "UMaskExt": "0xC80FFF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", > + "PerPkg": "1", > + "UMask": "0xC807FF01", > + "UMaskExt": "0xC807FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", > + "PerPkg": "1", > + "UMask": "0xC817FF01", > + "UMaskExt": "0xC817FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", > + "PerPkg": "1", > + "UMask": "0xC80FFF01", > + "UMaskExt": "0xC80FFF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", > + "PerPkg": "1", > + "UMask": "0xC816FE01", > + "UMaskExt": "0xC816FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", > + "PerPkg": "1", > + "UMask": "0xC8177E01", > + "UMaskExt": "0xC8177E", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", > + "PerPkg": "1", > + "UMask": "0xC816FE01", > + "UMaskExt": "0xC816FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", > + "PerPkg": "1", > + "UMask": "0xC8177E01", > + "UMaskExt": "0xC8177E", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", > + "PerPkg": "1", > + "UMask": "0xC896FE01", > + "UMaskExt": "0xC896FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", > + "PerPkg": "1", > + "UMask": "0xC8977E01", > + "UMaskExt": "0xC8977E", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", > + "PerPkg": "1", > + "UMask": "0xC806FE01", > + "UMaskExt": "0xC806FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", > + "PerPkg": "1", > + "UMask": "0xC8077E01", > + "UMaskExt": "0xC8077E", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", > + "PerPkg": "1", > + "UMask": "0xC886FE01", > + "UMaskExt": "0xC886FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", > + "PerPkg": "1", > + "UMask": "0xC8877E01", > + "UMaskExt": "0xC8877E", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", > + "PerPkg": "1", > + "UMask": "0xC8C7FF01", > + "UMaskExt": "0xC8C7FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", > + "PerPkg": "1", > + "UMask": "0xCC57FF01", > + "UMaskExt": "0xCC57FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", > + "PerPkg": "1", > + "UMask": "0xCD43FF04", > + "UMaskExt": "0xCD43FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", > + "PerPkg": "1", > + "UMask": "0xCD43FD04", > + "UMaskExt": "0xCD43FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", > + "PerPkg": "1", > + "UMask": "0xCD43FE04", > + "UMaskExt": "0xCD43FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", > + "PerPkg": "1", > + "UMask": "0xC8178A01", > + "UMaskExt": "0xC8178A", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", > + "PerPkg": "1", > + "UMask": "0xC8168A01", > + "UMaskExt": "0xC8168A", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", > + "PerPkg": "1", > + "UMask": "0xC8170A01", > + "UMaskExt": "0xC8170A", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", > + "PerPkg": "1", > + "UMask": "0xc867fe01", > + "UMaskExt": "0xc867fe", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts; WCiL misses from local IA", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", > + "PerPkg": "1", > + "UMask": "0xc86ffe01", > + "UMaskExt": "0xc86ffe", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", > + "PerPkg": "1", > + "UMask": "0xC8178A01", > + "UMaskExt": "0xC8178A", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", > + "PerPkg": "1", > + "UMask": "0xCCD7FE01", > + "UMaskExt": "0xCCD7FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", > + "PerPkg": "1", > + "UMask": "0xC8F3FE04", > + "UMaskExt": "0xC8F3FE", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", > + "PerPkg": "1", > + "UMask": "0xc8f3fe04", > + "UMaskExt": "0xc8f3fe", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", > + "PerPkg": "1", > + "UMask": "0xC8178601", > + "UMaskExt": "0xC81786", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", > + "PerPkg": "1", > + "UMask": "0xC8168601", > + "UMaskExt": "0xC81686", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", > + "PerPkg": "1", > + "UMask": "0xC8170601", > + "UMaskExt": "0xC81706", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", > + "PerPkg": "1", > + "UMask": "0xC8178601", > + "UMaskExt": "0xC81786", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", > + "PerPkg": "1", > + "UMask": "0xC8F3FD04", > + "UMaskExt": "0xC8F3FD", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", > + "PerPkg": "1", > + "UMask": "0xC8F3FF04", > + "UMaskExt": "0xC8F3FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x35", > + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", > + "PerPkg": "1", > + "UMask": "0xCCD7FF01", > + "UMaskExt": "0xCCD7FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices", > + "CounterType": "PGMABLE", > + "EventCode": "0x36", > + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", > + "PerPkg": "1", > + "UMask": "0xC8F3FF04", > + "UMaskExt": "0xC8F3FF", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x34", > + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", > + "PerPkg": "1", > + "UMask": "0x1BC1FF", > + "UMaskExt": "0x1BC1", > + "Unit": "CHA" > + }, > + { > + "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x01", > + "EventName": "UNC_IIO_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x01", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x02", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x04", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x08", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x01", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x02", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x04", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x08", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x01", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x02", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x04", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x08", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xC0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x01", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xC0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x02", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xC0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x04", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xC0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x08", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x01", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x02", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x04", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x08", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x01", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x02", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x04", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x08", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x01", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x02", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x04", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x08", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x01", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x02", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x04", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x08", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x01", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x02", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x04", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x08", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x01", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x02", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x04", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x08", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xC0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x10", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xC0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x20", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xC0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x40", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xC0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x80", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x10", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x20", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x40", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc0", > + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x80", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x10", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x20", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x40", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x80", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x10", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x20", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x40", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x80", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x10", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x20", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x40", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x83", > + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x80", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number requests PCIe makes of the main die : All", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x85", > + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0xFF", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x10", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x20", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x40", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x80", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x10", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x20", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x40", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc1", > + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x80", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x10", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x20", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x40", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x80", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x10", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x20", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x40", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x80", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x10", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x20", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x40", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x84", > + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", > + "FCMask": "0x07", > + "PerPkg": "1", > + "PortMask": "0x80", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Free running counter that increments for IIO clocktick", > + "CounterType": "FREERUN", > + "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", > + "PerPkg": "1", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc2", > + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", > + "FCMask": "0x04", > + "PerPkg": "1", > + "PortMask": "0x01", > + "UMask": "0x03", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc2", > + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", > + "FCMask": "0x04", > + "PerPkg": "1", > + "PortMask": "0x02", > + "UMask": "0x03", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc2", > + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", > + "FCMask": "0x04", > + "PerPkg": "1", > + "PortMask": "0x04", > + "UMask": "0x03", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc2", > + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", > + "FCMask": "0x04", > + "PerPkg": "1", > + "PortMask": "0x08", > + "UMask": "0x03", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc2", > + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", > + "FCMask": "0x04", > + "PerPkg": "1", > + "PortMask": "0x10", > + "UMask": "0x03", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc2", > + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", > + "FCMask": "0x04", > + "PerPkg": "1", > + "PortMask": "0x20", > + "UMask": "0x03", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc2", > + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", > + "FCMask": "0x04", > + "PerPkg": "1", > + "PortMask": "0x40", > + "UMask": "0x03", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc2", > + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", > + "FCMask": "0x04", > + "PerPkg": "1", > + "PortMask": "0x80", > + "UMask": "0x03", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xd5", > + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", > + "FCMask": "0x04", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xd5", > + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", > + "FCMask": "0x04", > + "PerPkg": "1", > + "UMask": "0x80", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xd5", > + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", > + "FCMask": "0x04", > + "PerPkg": "1", > + "UMask": "0x40", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xd5", > + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", > + "FCMask": "0x04", > + "PerPkg": "1", > + "UMask": "0x20", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xd5", > + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", > + "FCMask": "0x04", > + "PerPkg": "1", > + "UMask": "0x10", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xd5", > + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", > + "FCMask": "0x04", > + "PerPkg": "1", > + "UMask": "0x08", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xd5", > + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", > + "FCMask": "0x04", > + "PerPkg": "1", > + "UMask": "0x04", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xd5", > + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", > + "FCMask": "0x04", > + "PerPkg": "1", > + "UMask": "0x02", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc2", > + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", > + "FCMask": "0x04", > + "PerPkg": "1", > + "PortMask": "0xff", > + "UMask": "0x03", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", > + "Counter": "2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xd5", > + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", > + "FCMask": "0x04", > + "PerPkg": "1", > + "UMask": "0xff", > + "Unit": "IIO" > + }, > + { > + "BriefDescription": "Misc Events - Set 1 : Lost Forward", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x1F", > + "EventName": "UNC_I_MISC1.LOST_FWD", > + "PerPkg": "1", > + "UMask": "0x10", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x10", > + "EventName": "UNC_I_COHERENT_OPS.PCITOM", > + "PerPkg": "1", > + "UMask": "0x10", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": "Coherent Ops : WbMtoI", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x10", > + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", > + "PerPkg": "1", > + "UMask": "0x40", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x0f", > + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", > + "PerPkg": "1", > + "UMask": "0x04", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x20", > + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": "Inbound write (fast path) requests received by the IRP", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x11", > + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", > + "PerPkg": "1", > + "UMask": "0x08", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x01", > + "EventName": "UNC_I_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": "FAF RF full", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x17", > + "EventName": "UNC_I_FAF_FULL", > + "PerPkg": "1", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x18", > + "EventName": "UNC_I_FAF_INSERTS", > + "PerPkg": "1", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": "Occupancy of the IRP FAF queue", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x19", > + "EventName": "UNC_I_FAF_OCCUPANCY", > + "PerPkg": "1", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": "FAF allocation -- sent to ADQ", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x16", > + "EventName": "UNC_I_FAF_TRANSACTIONS", > + "PerPkg": "1", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", > + "Counter": "0,1", > + "CounterType": "PGMABLE", > + "EventCode": "0x12", > + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", > + "PerPkg": "1", > + "UMask": "0x78", > + "Unit": "IRP" > + }, > + { > + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x2D", > + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "M2M" > + }, > + { > + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x2D", > + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", > + "PerPkg": "1", > + "UMask": "0x08", > + "Unit": "M2M" > + }, > + { > + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x2D", > + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", > + "PerPkg": "1", > + "UMask": "0x02", > + "Unit": "M2M" > + }, > + { > + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x2D", > + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", > + "PerPkg": "1", > + "UMask": "0x04", > + "Unit": "M2M" > + }, > + { > + "BriefDescription": "Tag Hit : Clean NearMem Read Hit", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x2C", > + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", > + "PerPkg": "1", > + "UMask": "0x01", > + "Unit": "M2M" > + }, > + { > + "BriefDescription": "Tag Hit : Dirty NearMem Read Hit", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x2C", > + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", > + "PerPkg": "1", > + "UMask": "0x02", > + "Unit": "M2M" > + }, > + { > + "BriefDescription": "Clockticks of the mesh to memory (M2M)", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventName": "UNC_M2M_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "M2M" > + }, > + { > + "BriefDescription": "CMS Clockticks", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc0", > + "EventName": "UNC_M2M_CMS_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "M2M" > + }, > + { > + "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x37", > + "EventName": "UNC_M2M_IMC_READS.TO_PMM", > + "PerPkg": "1", > + "UMask": "0x0720", > + "UMaskExt": "0x07", > + "Unit": "M2M" > + }, > + { > + "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x38", > + "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", > + "PerPkg": "1", > + "UMask": "0x1C80", > + "UMaskExt": "0x1C", > + "Unit": "M2M" > + }, > + { > + "BriefDescription": "Clockticks of the mesh to PCI (M2P)", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x01", > + "EventName": "UNC_M2P_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "M2PCIe" > + }, > + { > + "BriefDescription": "CMS Clockticks", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0xc0", > + "EventName": "UNC_M2P_CMS_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "M2PCIe" > + }, > + { > + "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x01", > + "EventName": "UNC_M3UPI_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "M3UPI" > + }, > + { > + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", > + "Counter": "FIXED", > + "CounterType": "FIXED", > + "EventCode": "0xff", > + "EventName": "UNC_U_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "UBOX" > + }, > + { > + "BriefDescription": "Valid Flits Received : All Data", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x03", > + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", > + "PerPkg": "1", > + "UMask": "0x0F", > + "Unit": "UPI LL" > + }, > + { > + "BriefDescription": "Valid Flits Received : All Non Data", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x03", > + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", > + "PerPkg": "1", > + "UMask": "0x97", > + "Unit": "UPI LL" > + }, > + { > + "BriefDescription": "Valid Flits Sent : All Data", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x02", > + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", > + "PerPkg": "1", > + "UMask": "0x0F", > + "Unit": "UPI LL" > + }, > + { > + "BriefDescription": "Valid Flits Sent : All Non Data", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x02", > + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", > + "PerPkg": "1", > + "UMask": "0x97", > + "Unit": "UPI LL" > + }, > + { > + "BriefDescription": "Number of kfclks", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x01", > + "EventName": "UNC_UPI_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "UPI LL" > + }, > + { > + "BriefDescription": "Cycles in L1", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x21", > + "EventName": "UNC_UPI_L1_POWER_CYCLES", > + "PerPkg": "1", > + "Unit": "UPI LL" > + }, > + { > + "BriefDescription": "Cycles in L0p", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x27", > + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", > + "PerPkg": "1", > + "Unit": "UPI LL" > + }, > + { > + "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x02", > + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", > + "PerPkg": "1", > + "UMask": "0x27", > + "Unit": "UPI LL" > + }, > + { > + "BriefDescription": "Valid Flits Received : Null FLITs received from any slot", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventCode": "0x03", > + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", > + "PerPkg": "1", > + "UMask": "0x27", > + "Unit": "UPI LL" > + } > +] > diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json > new file mode 100644 > index 000000000000..2d1368958762 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json > @@ -0,0 +1,10 @@ > +[ > + { > + "BriefDescription": "Clockticks of the power control unit (PCU)", > + "Counter": "0,1,2,3", > + "CounterType": "PGMABLE", > + "EventName": "UNC_P_CLOCKTICKS", > + "PerPkg": "1", > + "Unit": "PCU" > + } > +] > -- > 2.17.1 >