Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp1393720pxj; Fri, 21 May 2021 13:08:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjywyP+Ec0eZ3BY+uGmbNAvI6QayPbrEDlEt/I/91AymhIJhSimsmHg9fin8YAWIypVEoH X-Received: by 2002:a02:b90b:: with SMTP id v11mr6770703jan.1.1621627735711; Fri, 21 May 2021 13:08:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621627735; cv=none; d=google.com; s=arc-20160816; b=g16teldpsMZFybwQd6L2RAodXrbjumdn2Mmof3cZgimKrEU4tP+5ki1qwXuNxNCMFT 1Y8ZaWDIWuxyesBqob/tLlbwOf+fBd0AJsWRv0BCYBeVVvWiIl0i4VASJ46td2nzsUg0 yu3n1zHJQRMMBYTrGPSqx8ze5wfINZBVFDR8Zzln+PqbhEjUsYkU/h4mfmtUVhk9N4Pw TpLlxNM/NOC71xrzxedFP1vQCtihm1FHdavDmrwHiPCGD/q/NTL1A5ouTnVB6tR8U2AC wYUQICjl1Bw7Ix7NielHAQlaFnkGe0F0umf5ZcqwNNPRWNE9A8wU872UB3/Cgw+pwixw rW4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:content-language :in-reply-to:mime-version:user-agent:date:message-id:from:references :cc:to:subject; bh=3HWv07kk/ksFwqy/USTxTx/BcKirWQJQLRvi6828KfA=; b=JEdQr51sk51iDRf+rry1gQW/ZZr7inOFcLuGMcZtbvZGvhnedJILNY3PORf5awjyyC 5PbjMQBTgesgBHuWxTy73Mm1O+3siKOmF7cXmu4bRKRnLyKWuAhu1eyPsPyPctMd4uhW cLjN8TYoefHnKQ+B7+ZVeGWra9U3h8AluggPl3Mz5sbPJabhnRqibKblEIGPB7kvEEe9 Ki+96s5/l/l+aCjq8X7M4AL/FWrEvRWer4BsIMmTxkTr/1hH8ZhvAvozpfk3sYW+ph9t qc3Zv2L7WlD31uQMRcr9xGGkm5NnSAbFvWhPMW8w1TUs8UBTKU8jzO1Qb73CChD9f4Pi kEdw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r12si1290950ilg.107.2021.05.21.13.08.43; Fri, 21 May 2021 13:08:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233598AbhEUGpc (ORCPT + 99 others); Fri, 21 May 2021 02:45:32 -0400 Received: from mleia.com ([178.79.152.223]:54460 "EHLO mail.mleia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233240AbhEUGpa (ORCPT ); Fri, 21 May 2021 02:45:30 -0400 Received: from mail.mleia.com (localhost [127.0.0.1]) by mail.mleia.com (Postfix) with ESMTP id 6F5943990; Fri, 21 May 2021 06:44:07 +0000 (UTC) Subject: Re: [PATCH v3 2/3] pinctrl: core: configure pinmux from pins debug file To: Dario Binacchi , linux-kernel@vger.kernel.org Cc: Tony Lindgren , Drew Fustini , Linus Walleij , Andy Shevchenko , linux-gpio@vger.kernel.org References: <20210520202730.4444-1-dariobin@libero.it> <20210520202730.4444-3-dariobin@libero.it> From: Vladimir Zapolskiy Message-ID: <87ea9971-9e15-c595-95cc-14c68b0b68d8@mleia.com> Date: Fri, 21 May 2021 09:44:06 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.1 MIME-Version: 1.0 In-Reply-To: <20210520202730.4444-3-dariobin@libero.it> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-49551924 X-CRM114-CacheID: sfid-20210521_064407_482056_69BD8F55 X-CRM114-Status: GOOD ( 11.19 ) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Dario, On 5/20/21 11:27 PM, Dario Binacchi wrote: > The MPUs of some architectures (e.g AM335x) must be in privileged > operating mode to write on the pinmux registers. In such cases, where > writes will not work from user space, now it can be done from the pins user space has no connection to the problem you're trying to solve. Please provide a reasonable rationale for adding a new interface, thank you in advance. > debug file if the platform driver exports the pin_dbg_set() helper among > the registered operations. > > Signed-off-by: Dario Binacchi I strongly object against this new interface. As Andy've already mentioned you have to operate with defined pin groups and functions, and so far you create an interface with an option to disasterous misusage, it shall be avoided, because there are better options. What's the issue with a regular declaration of pin groups and functions on your SoC? When it's done, you can operate on this level of abstraction, there is absolutely no need to add the proposed low-level debug interface. -- Best wishes, Vladimir