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[174.61.140.56]) by smtp.gmail.com with ESMTPSA id q3sm3914489pff.142.2021.05.21.01.59.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 01:59:20 -0700 (PDT) From: Joe Richey To: trivial@kernel.org Cc: Joe Richey , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" , Paolo Bonzini , Mark Rutland , Lorenzo Pieralisi , Mauro Carvalho Chehab , Zhangfei Gao , Zhou Wang , Andy Whitcroft , Joe Perches , Dwaipayan Ray , Lukas Bulwahn , Sasha Levin , "Chang S. Bae" , Andi Kleen , Lei Cao , Peter Xu , Daniel Lezcano , Ulf Hansson , "Rafael J. Wysocki" , Jean-Philippe Brucker , Zaibo Xu , Kenneth Lee , Greg Kroah-Hartman , Hans Verkuil , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-accelerators@lists.ozlabs.org Subject: [PATCH v2 3/7] drivers: firmware: psci: Use _BITUL() macro in UAPI headers Date: Fri, 21 May 2021 01:58:44 -0700 Message-Id: <20210521085849.37676-4-joerichey94@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210521085849.37676-1-joerichey94@gmail.com> References: <20210520104343.317119-1-joerichey94@gmail.com> <20210521085849.37676-1-joerichey94@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Joe Richey Replace BIT() in psci's UPAI header with _BITUL(). BIT() is not defined in the UAPI headers and its usage may cause userspace build errors. Fixes: 60dd1ead65e8 ("drivers: firmware: psci: Announce support for OS initiated suspend mode") Signed-off-by: Joe Richey --- include/uapi/linux/psci.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/psci.h b/include/uapi/linux/psci.h index 2fcad1dd0b0e..87afdeb95096 100644 --- a/include/uapi/linux/psci.h +++ b/include/uapi/linux/psci.h @@ -12,6 +12,8 @@ #ifndef _UAPI_LINUX_PSCI_H #define _UAPI_LINUX_PSCI_H +#include + /* * PSCI v0.1 interface * @@ -100,7 +102,7 @@ #define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_MASK \ (0x1 << PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT) -#define PSCI_1_0_OS_INITIATED BIT(0) +#define PSCI_1_0_OS_INITIATED _BITUL(0) #define PSCI_1_0_SUSPEND_MODE_PC 0 #define PSCI_1_0_SUSPEND_MODE_OSI 1 -- 2.31.1