Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp1403949pxj; Fri, 21 May 2021 13:25:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy+KL0GNhdiIkHBuJDl41Amf++KSaCvHLYN0aMXKFgQUjKB6+bAXtMFhHAozoP+C06hzu8A X-Received: by 2002:a92:6610:: with SMTP id a16mr683083ilc.124.1621628734261; Fri, 21 May 2021 13:25:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621628734; cv=none; d=google.com; s=arc-20160816; b=HwBRMdrmXnev6jSYDyqGT6gyUurXMq2I25RvleRA/1nzR05ituSDvUX+D3idaBymPB vasz69HJ4meMtwAMsLc+UBX5SPoTKL25KJXfut70zYmeYzopaVo0bImUvwkJcITpopNR gQJ3O71E1ZbNlPMGHu232XztYIX7fNiEY/eDUvftktkr/IZ3kD6VZ2fsbsykJ1u+RiBv L7xswEES5XKxttabbwN/b9ZOdWXRHgQnNiJ+NYxyoWu1mjk/Sw9hRHrElyh8UoF9UQrV KSluGh7WkZpwsZzd/4kEaReGHO32Eeumdm0n5O88evMr8PSYWu5nlXRPJqi9lG8S8QdC 3IDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=/PGMSdzY46rRUuH9CGjzhpvBKwl08kAKQs9u+i9AHgw=; b=V33Wxw9lkpd8aO4lf7j67Uasewx2JZtrgdH2qLq9CRM4sb9PWPFjg/F5S6LU08hNon 0IIfBz7/Yy8jlwoPFAbEjQSSWrE5Hu/iw0hmSvhGj/jFy5a5oRvgCDQhaoseQL25V6tm Di/KPeRkdCfCf8K+7ZrghjUADvDuju6G9Rs9M1hYeKJbLMHzDD6BM38NovHyLhyThtYV xDr3R88mPyNKMiayZs0Ixfd6q+Kl7oW8KSY5I3MV9D06ZdbI+noF8Vv/9W450ErCsMcf /jOMMusio+rzImVXYVFrZ1Hw6DwPBLUXtw2xQFLuVyRX99xBLrJHnMQ2CgPY/BbIpADP zDIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@raspberrypi.com header.s=google header.b="Nn/JXXpz"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=raspberrypi.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m12si6333390jav.104.2021.05.21.13.25.16; Fri, 21 May 2021 13:25:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@raspberrypi.com header.s=google header.b="Nn/JXXpz"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=raspberrypi.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233155AbhEURlS (ORCPT + 99 others); Fri, 21 May 2021 13:41:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238282AbhEURlG (ORCPT ); Fri, 21 May 2021 13:41:06 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6B65C061574 for ; Fri, 21 May 2021 10:39:41 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id l18-20020a1ced120000b029014c1adff1edso7841337wmh.4 for ; Fri, 21 May 2021 10:39:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raspberrypi.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/PGMSdzY46rRUuH9CGjzhpvBKwl08kAKQs9u+i9AHgw=; b=Nn/JXXpzFSUUF64vgcRuuSVXe/enfhqmlOCjKV5fks10W3PXjnVsUKNxAZt2HMHBNP wp1MYjFhmTKcFLOLG8SjGSwkRr/JmWL2ygPv97tNoCrECDCzHaxms1bNUwOc2dBrG3yA dwrN2LsP9pod4hYOFhawoiW8PNKgurFDMx3m+vJCAciOjFkSzs4QR1/8Ao6FKSuR9VnQ hT/AQU6r8/9UNqBRPIJW4Wp+Oomm9NrER4XqbAOs4p2GLScxEUkSP1OvV8S1qMHAW1nX AuOzbK/cC9MOhbsgp6XnaF1p//DBJAUkCQvlZY6Wca1KMeo0SOwrWrmiKl8kT0lp9JG9 J35w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/PGMSdzY46rRUuH9CGjzhpvBKwl08kAKQs9u+i9AHgw=; b=N3A/ynMXRYxHCf6R0qQO5Tl//A6PLHMqK0oLwrQW/GNjJW0+of6OpYJ84DYga2s/R9 MulDAH+2fY0NVU7eL03Ks6UZXFtz08WoWrLddl9HJf3tUHyuBUNoNCPOUCwl8kaq/ld4 2Qbu8q0Q1Xe5IjBr02EBjQKnQBhefo8QFay9dCUbmcbw78jyM2DMaarZM1xjdPc7jzEl 6JOa1cajukHInW2VmnrYvf3NtUgHivb9bBhTGxDtpbJioHBEWqHbLmZY6TOr362Ax0q1 nXbkOnAXGVaZTKPUOXs0AMAujO7kNvs7eIUKK0QIBLjrid0k3xVOekxVgbNWvZTMhMMq LavA== X-Gm-Message-State: AOAM531O+q6B0QqQY7Rm+97hZr8rrne3+aEkk6fBjuTj36oeXCpO5OzB 1dn8mWhF1FPaq5hJvoTVW28NoZEDomkqu530y1Pv8g== X-Received: by 2002:a7b:cbc2:: with SMTP id n2mr10189003wmi.116.1621618780301; Fri, 21 May 2021 10:39:40 -0700 (PDT) MIME-Version: 1.0 References: <20210507150515.257424-1-maxime@cerno.tech> <20210507150515.257424-11-maxime@cerno.tech> In-Reply-To: <20210507150515.257424-11-maxime@cerno.tech> From: Dave Stevenson Date: Fri, 21 May 2021 18:39:24 +0100 Message-ID: Subject: Re: [PATCH v4 10/12] drm/vc4: hdmi: Enable the scrambler To: Maxime Ripard Cc: Maarten Lankhorst , Thomas Zimmermann , DRI Development , Daniel Vetter , David Airlie , Eric Anholt , Nicolas Saenz Julienne , bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, Phil Elwell , Tim Gover , Dom Cobley , LKML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Maxime On Fri, 7 May 2021 at 16:06, Maxime Ripard wrote: > > The HDMI controller on the BCM2711 includes a scrambler in order to > reach the HDMI 2.0 modes that require it. Let's add the support for it. > > Acked-by: Thomas Zimmermann > Signed-off-by: Maxime Ripard Reviewed-by: Dave Stevenson > --- > drivers/gpu/drm/vc4/vc4_hdmi.c | 64 +++++++++++++++++++++++++++++ > drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 3 ++ > 2 files changed, 67 insertions(+) > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index 01d24ce8a795..bda12fea0dce 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -35,6 +35,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -76,6 +77,8 @@ > #define VC5_HDMI_VERTB_VSPO_SHIFT 16 > #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) > > +#define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) > + > #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 > #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) > > @@ -462,6 +465,64 @@ static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) > vc4_hdmi_set_audio_infoframe(encoder); > } > > +static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, > + struct drm_display_mode *mode) > +{ > + struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); > + struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > + struct drm_display_info *display = &vc4_hdmi->connector.display_info; > + > + if (!vc4_encoder->hdmi_monitor) > + return false; > + > + if (!display->hdmi.scdc.supported || > + !display->hdmi.scdc.scrambling.supported) > + return false; > + > + return true; > +} > + > +static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) > +{ > + struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; > + struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > + > + if (!vc4_hdmi_supports_scrambling(encoder, mode)) > + return; > + > + if (!vc4_hdmi_mode_needs_scrambling(mode)) > + return; > + > + drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); > + drm_scdc_set_scrambling(vc4_hdmi->ddc, true); > + > + HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | > + VC5_HDMI_SCRAMBLER_CTL_ENABLE); > +} > + > +static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) > +{ > + struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > + struct drm_crtc *crtc = encoder->crtc; > + > + /* > + * At boot, encoder->crtc will be NULL. Since we don't know the > + * state of the scrambler and in order to avoid any > + * inconsistency, let's disable it all the time. > + */ > + if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode)) > + return; > + > + if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode)) > + return; > + > + HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & > + ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); > + > + drm_scdc_set_scrambling(vc4_hdmi->ddc, false); > + drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); > +} > + > static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, > struct drm_atomic_state *state) > { > @@ -474,6 +535,8 @@ static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, > > HDMI_WRITE(HDMI_VID_CTL, > HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); > + > + vc4_hdmi_disable_scrambling(encoder); > } > > static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, > @@ -924,6 +987,7 @@ static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, > } > > vc4_hdmi_recenter_fifo(vc4_hdmi); > + vc4_hdmi_enable_scrambling(encoder); > } > > static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h > index e1b58eac766f..19d2fdc446bc 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h > +++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h > @@ -100,6 +100,7 @@ enum vc4_hdmi_field { > HDMI_RM_FORMAT, > HDMI_RM_OFFSET, > HDMI_SCHEDULER_CONTROL, > + HDMI_SCRAMBLER_CTL, > HDMI_SW_RESET_CONTROL, > HDMI_TX_PHY_CHANNEL_SWAP, > HDMI_TX_PHY_CLK_DIV, > @@ -238,6 +239,7 @@ static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = { > VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178), > VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c), > VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8), > + VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4), > > VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc), > VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0), > @@ -317,6 +319,7 @@ static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = { > VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178), > VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c), > VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8), > + VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4), > > VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc), > VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0), > -- > 2.31.1 >