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[23.128.96.18]) by mx.google.com with ESMTP id w3si6647181iov.75.2021.05.21.13.44.31; Fri, 21 May 2021 13:44:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=aaLl3EF2; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237896AbhEUTLz (ORCPT + 99 others); Fri, 21 May 2021 15:11:55 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:55838 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234402AbhEUTLy (ORCPT ); Fri, 21 May 2021 15:11:54 -0400 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1621624230; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+06u+wdZEMxW6NyWmiNO0gVYIZ0+Re0+Y3ZmGldgwNc=; b=aaLl3EF2IgQnaSKKg1nxYMUJzsvLzbxaaLESyykkrwUQQ3XG8zEV2QFFm1+4uyf4OtkOEU blNSgH8NS5lOyUf/Zhg6cl38LntdeDIKu/xHEtkRXCUzm0fqiFqW+wy/mrj2emvPci7KXi h2/LQPAy8CUHrsL/L9YplBtsJ7P0U+ytWCcgMyY4xdoN9gD1hCJx0HgOiLFhPykNyyAkL8 AYwELp2txsrvyG3du+fFCJWZ/CrEPT/nXlJqsMHo0fw9V3H1/qwYCTHqERTe6yErlRQOqA qpO23fsKqseiXxmZQ6v1vNGuL2uqqtEczwvdCoNJIiFgSOjL8K7pTUockbGAWw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1621624230; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+06u+wdZEMxW6NyWmiNO0gVYIZ0+Re0+Y3ZmGldgwNc=; b=BuI+lIrOiz4aW1b3y5gyTkQmeZ3pQt+NK9nUepZLAoHA92B9QOS/3XH+sT9XY7q66mgtI1 FHEigHsXuexcOiBw== To: Andy Lutomirski , Florian Weimer , Dave Hansen Cc: Dave Hansen via Libc-alpha , Len Brown , Rich Felker , Linux API , "Bae\, Chang Seok" , the arch/x86 maintainers , Linux Kernel Mailing List , Kyle Huey , Borislav Petkov , Keno Fischer , Arjan van de Ven , Willy Tarreau Subject: Re: Candidate Linux ABI for Intel AMX and hypothetical new related features In-Reply-To: <263a58a9-26d5-4e55-b3e1-3718baf1b81d@www.fastmail.com> References: <20210415044258.GA6318@zn.tnic> <20210415054713.GB6318@zn.tnic> <20210419141454.GE9093@zn.tnic> <20210419191539.GH9093@zn.tnic> <20210419215809.GJ9093@zn.tnic> <874kf11yoz.ffs@nanos.tec.linutronix.de> <87k0ntazyn.ffs@nanos.tec.linutronix.de> <37833625-3e6b-5d93-cc4d-26164d06a0c6@intel.com> <9c8138eb-3956-e897-ed4e-426bf6663c11@intel.com> <87pmxk87th.fsf@oldenburg.str.redhat.com> <939ec057-3851-d8fb-7b45-993fa07c4cb5@intel.com> <87r1i06ow2.fsf@oldenburg.str.redhat.com> <263a58a9-26d5-4e55-b3e1-3718baf1b81d@www.fastmail.com> Date: Fri, 21 May 2021 21:10:29 +0200 Message-ID: <87k0nraonu.ffs@nanos.tec.linutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, May 21 2021 at 09:31, Andy Lutomirski wrote: > arch_prctl(SET_XSTATE_INIT_ON_FIRST_USE, TILE_STUFF);? > > As long as this is allowed to fail, I don=E2=80=99t have a huge problem w= ith > it. I'm fine with that. It's still controlled by the OS and can return -EPERM. If allowed then the application would also accept to be insta killed if that #NM allocation fails. Any bug report vs. that will be ignored. > I think several things here are regrettable: > > 1. Legacy XSTATE code might assume that XCR0 is a constant. > > 2. Intel virt really doesn=E2=80=99t like us context switching XCR0, alth= ough > we might say that this is Intel=E2=80=99s fault and therefore Intel=E2=80= =99s > problem. AMD hardware doesn=E2=80=99t appear to have this issue. > > 3. AMX bring tangled up in XSTATE is unfortunate. The whole XSTATE > mechanism is less than amazing. > > IMO the best we can make of this whole situation is to make XCR0 > dynamic, but the legacy compatibility issues are potentially > problematic. Why? The bit can be enabled and #NM catches the violation of the ABI contract if the application did not request usage. No XCR0 fiddling on context switch required. Thanks, tglx