Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp3438603pxj; Mon, 24 May 2021 06:50:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJykuaxmE9CVHq0tR4TXNQE6u7OWe3SaNRue+258CCITPN5emflm08BlWgnSL8WJTvsNYmZ4 X-Received: by 2002:a92:cc43:: with SMTP id t3mr19005914ilq.250.1621864228413; Mon, 24 May 2021 06:50:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621864228; cv=none; d=google.com; s=arc-20160816; b=v+ZyLk4vN0Pp5GtiQ+6O5tudvct9gVxrGaFCDCvx/ESubfBi6PKONhEOhrGEyYqi/z EsTxcTVR4ZsffTqnSVJicXtJuFi63nLR6paFgciqn8nm0ROgCnvs4vhRkVCxwEu8WtyI gDieOeLYUnNacqYjnTLeywlBXf8+c+OUv8YbiWp3zrhZXJiPl+wVRy9hZiRI2erLMSwc 2cYyUBt35kd22dkqdF96UiqB+0KF9xfTQdNN9YPpV0mH4kjPXHope9PjtkKjf02GaWpi UerbvcqTRbLG6ngHORv4zvSZSbacF8LEeJKsH6y7BfxpVBnIzU1M9PzL+Eie3rbkMJwM Q7UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=JROytCSrnA4vDJyccuaodWObwB5NU8MpbC8ruOyktGU=; b=V8EHZyRQr0uSpsw3dIi+XGleYfh3IuXKYl/6BX0m/XfOTEhatDFA1ZN4QHwp16cl8v DzXUy3riOQDikZB0Iv0A4V+kxKuSCEKZxEVEzaHG4hlHtuTW4fln/qXRuBRB6OM/EjPG Txq3Ce1qn3NupKmLkGUxA7eOSKYjJU+p+ctGgqnaPFYMefgQqKoH8WtE9Rb1mcZN5WEj X47x/DPymCs6sKvdkjJ5NmpmlU2S+g9C0BdS6SBU2LGSlQQowMsSb3cwpBcUIKG0wQE/ 9oNyIT5W5uDYEyybSckPwHcKdwfAgGu0EAnz7uev9fQf8BhPk/fQzk+pyhV3CbiqNRB9 b9jA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j2si228518ilr.133.2021.05.24.06.50.15; Mon, 24 May 2021 06:50:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232685AbhEXNuz (ORCPT + 99 others); Mon, 24 May 2021 09:50:55 -0400 Received: from mail.kernel.org ([198.145.29.99]:41788 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232409AbhEXNuy (ORCPT ); Mon, 24 May 2021 09:50:54 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8A67761370; Mon, 24 May 2021 13:49:23 +0000 (UTC) Date: Mon, 24 May 2021 14:49:21 +0100 From: Catalin Marinas To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Qais Yousef , Suren Baghdasaryan , Quentin Perret , Tejun Heo , Li Zefan , Johannes Weiner , Ingo Molnar , Juri Lelli , Vincent Guittot , "Rafael J. Wysocki" , kernel-team@android.com Subject: Re: [PATCH v6 02/21] arm64: Allow mismatched 32-bit EL0 support Message-ID: <20210524134920.GB14645@arm.com> References: <20210518094725.7701-1-will@kernel.org> <20210518094725.7701-3-will@kernel.org> <20210521102523.GB6675@arm.com> <20210524120550.GA14913@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210524120550.GA14913@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 24, 2021 at 01:05:50PM +0100, Will Deacon wrote: > On Fri, May 21, 2021 at 11:25:23AM +0100, Catalin Marinas wrote: > > On Tue, May 18, 2021 at 10:47:06AM +0100, Will Deacon wrote: > > > +static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) > > > +{ > > > + if (!has_cpuid_feature(entry, scope)) > > > + return allow_mismatched_32bit_el0; > > > + > > > + if (scope == SCOPE_SYSTEM) > > > + pr_info("detected: 32-bit EL0 Support\n"); > > > + > > > + return true; > > > +} > > > > We may have discussed this before: AFAICT this will print 32-bit EL0 > > detected even if there's no 32-bit EL0 on any CPU. Should we instead > > print 32-bit EL0 detected on CPU X when allow_mismatched_32bit_el0 is > > passed? It would also give us an indication of the system configuration > > when people start reporting bugs. > > The function above only runs if we've detected 32-bit support via > aa64pfr0_el1, so I think we're ok. We also have a print when we detect the > mismatch (see enable_mismatched_32bit_el0()). It makes sense, you removed the .desc from the arm64_features entry as well. Reviewed-by: Catalin Marinas