Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp3551539pxj; Mon, 24 May 2021 09:11:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxBVI0MPfHdPutfNTwxTXbOAt6BlRvSivu6kV70K3vm3ZIjpHRw6P/r8GsaJpo5L5ks3q0w X-Received: by 2002:a05:6602:2b8b:: with SMTP id r11mr2163902iov.129.1621872690627; Mon, 24 May 2021 09:11:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621872690; cv=none; d=google.com; s=arc-20160816; b=fglrfoTAnnQe7lLsGC2QsuMTBVaZoQr6cVqH05XFlcNv8iH03k47kMi4OBkU/LQ9F0 cYUBLLpaH/qJbFl+zLo4F/zuI4C9NeyNUyhs+Yy4HtoYJnNQX3L/Eca3IWW9QlhrMkVA oqqll/x7AinKJ07wxhDt8Pe3kOd7KK6JC035XiWC6b0Cj1JoNvla5ctWYXcAsKk0du1r xW0Qj3f99lnBZX6798SWxlgtDZOJDU47RD+O4uH4wYGXpBEu0k4n4wOy5kz7enbd+Bsz ODZMD1BZmqB3gJ7vwSQ82nZCLdLREm4zG2jyyOm9n0yxxa0UsT1QhugknLI0Lxrtu5uk GDcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=6Oy5lHtoQJwic9trlhzu0oTNe6OfMomGzvbD6vZU+LA=; b=zFaVw3kSiWUBoo68LKundD9g/Y8lyR9dxEPb54KBB5xDQJ8PX5Lhqp3uQz7HTK5d0+ CIbPZ2nS/tp7+EUgSjHvNOBL0nk54hQyFHZZlOjFYV1XIQ1/edOCOuyFDlztCdMDsJ09 Ct2HcLEkr2zOzTJVJTyu57VdpPzqpXKxvC06nkvftVvEqant1U5MGAHgpFagA/50QA/0 Z+o3hb38ZcNy7OuF0E/qj2jQvRMpAekDZ4YskXYeXZpMr8ibiHOyxDTg4rB5nBzbQNSe vmJQFQwwvTpSDOH9/APN985xm1xalgdojdss5X+377DfdFo1P2ymIahr585ScoNpm8Po 9NcQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m12si14404070ild.137.2021.05.24.09.11.17; Mon, 24 May 2021 09:11:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238667AbhEXQKR (ORCPT + 99 others); Mon, 24 May 2021 12:10:17 -0400 Received: from mail.kernel.org ([198.145.29.99]:47738 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233469AbhEXQCO (ORCPT ); Mon, 24 May 2021 12:02:14 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 90DBA6199C; Mon, 24 May 2021 15:47:00 +0000 (UTC) Date: Mon, 24 May 2021 16:46:58 +0100 From: Catalin Marinas To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Qais Yousef , Suren Baghdasaryan , Quentin Perret , Tejun Heo , Li Zefan , Johannes Weiner , Ingo Molnar , Juri Lelli , Vincent Guittot , "Rafael J. Wysocki" , kernel-team@android.com Subject: Re: [PATCH v6 18/21] arm64: Prevent offlining first CPU with 32-bit EL0 on mismatched system Message-ID: <20210524154657.GE14645@arm.com> References: <20210518094725.7701-1-will@kernel.org> <20210518094725.7701-19-will@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210518094725.7701-19-will@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 18, 2021 at 10:47:22AM +0100, Will Deacon wrote: > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 959442f76ed7..72efdc611b14 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2896,15 +2896,33 @@ void __init setup_cpu_features(void) > > static int enable_mismatched_32bit_el0(unsigned int cpu) > { > + static int lucky_winner = -1; > + > struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); > bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); > > if (cpu_32bit) { > cpumask_set_cpu(cpu, cpu_32bit_el0_mask); > static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); > - setup_elf_hwcaps(compat_elf_hwcaps); > } > > + if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) > + return 0; I don't fully understand this early return. AFAICT, we still call setup_elf_hwcaps() via setup_cpu_features() if the system supports 32-bit EL0 (mismatched or not) at boot. For CPU hotplug, we can add the compat hwcaps later if we didn't set them up at boot. So this part is fine. However, if CPU0 is 32-bit-capable, it looks like we'd never disable the offlining on any of the 32-bit-capable CPUs and there's nothing that prevents offlining CPU0. -- Catalin