Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
MIME-Version: 1.0
References: <20210523193259.26200-1-chang.seok.bae@intel.com>
 <20210523193259.26200-29-chang.seok.bae@intel.com> <fd9ea1d5-06cf-c5e7-e44e-d74fa7627983@intel.com>
In-Reply-To: <fd9ea1d5-06cf-c5e7-e44e-d74fa7627983@intel.com>
From:   Len Brown <lenb@kernel.org>
Date:   Mon, 24 May 2021 13:34:28 -0400
Message-ID: <CAJvTdKk-53JzUzgGbgWSsfMcGPjQ0Wvrb-AqYOhX3JArVsB=Qg@mail.gmail.com>
Subject: Re: [PATCH v5 28/28] x86/fpu/amx: Clear the AMX state when appropriate
To:     Dave Hansen <dave.hansen@intel.com>
Cc:     "Chang S. Bae" <chang.seok.bae@intel.com>,
        Borislav Petkov <bp@suse.de>,
        Andy Lutomirski <luto@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@kernel.org>, X86 ML <x86@kernel.org>,
        "Brown, Len" <len.brown@intel.com>,
        "Liu, Jing2" <jing2.liu@intel.com>,
        "Ravi V. Shankar" <ravi.v.shankar@intel.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

On Mon, May 24, 2021 at 10:07 AM Dave Hansen <dave.hansen@intel.com> wrote:

> Could we maybe say:
>
>                 /*
>                  * Leaving state in the TILE registers may prevent the
>                  * processor from entering low-power idle states.  Use
>                  * TILERELEASE to initialize the state.  Destroying
>                  * fpregs state is safe after the fpstate update.
>                  */

Ack

> Also, referencing fpregs/fpstate is really nice because the codes
> doesn't actually say "XSAVE" anywhere.
>
> > +             if (fpu->state_mask & XFEATURE_MASK_XTILE_DATA)
> > +                     tile_release();
>
> Doesn't this tile_release() need a fpregs_deactivate()?  Otherwise, the
> next XRSTOR might get optimized away because it thinks there's still
> good data in the fpregs.
>
> Will this unnecessarily thwart the modified optimization in cases where
> we go and run this task again without ever going out to userspace?  Will
> this impact context-switch latency for *EVERY* context switch in order
> to go to a lower idle state in a few minutes, hours, or never?

yeah, seems we missed that.


thanks!
Len Brown, Intel Open Source Technology Center