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From:   "Chang S. Bae" <chang.seok.bae@intel.com>
To:     luto@kernel.org, dave.hansen@intel.com, lenb@kernel.org
Cc:     bp@suse.de, tglx@linutronix.de, mingo@kernel.org, x86@kernel.org,
        len.brown@intel.com, jing2.liu@intel.com, ravi.v.shankar@intel.com,
        linux-kernel@vger.kernel.org, chang.seok.bae@intel.com
Subject: [PATCH v5-fix 28/28] x86/fpu/amx: Clear the AMX state when appropriate
Date:   Mon, 24 May 2021 14:11:00 -0700
Message-Id: <20210524211100.3347-1-chang.seok.bae@intel.com>
In-Reply-To: <CAJvTdKk-53JzUzgGbgWSsfMcGPjQ0Wvrb-AqYOhX3JArVsB=Qg@mail.gmail.com>
References: <CAJvTdKk-53JzUzgGbgWSsfMcGPjQ0Wvrb-AqYOhX3JArVsB=Qg@mail.gmail.com>
Precedence: bulk

When AMX is enabled, and an AMX-task is saved, explicitly initialize the
AMX state after the XSAVE.

This assures that the kernel will only request idle states with clean AMX
state. In the case of the C6 idle state, this allows the hardware to get to
a deeper power saving condition.

Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
---
Changes from v5:
* Fixed to deactivate fpregs. (Andy Lutomirski and Dave Hansen)
* Updated the code comment. (Dave Hansen)

Changes from v4:
* Added as a new patch. (Thomas Gleixner)
---
 arch/x86/include/asm/special_insns.h |  6 ++++++
 arch/x86/kernel/fpu/core.c           | 11 +++++++++++
 2 files changed, 17 insertions(+)

diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
index 2acd6cb62328..f0ed063035eb 100644
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -306,6 +306,12 @@ static inline int enqcmds(void __iomem *dst, const void *src)
 	return 0;
 }
 
+static inline void tile_release(void)
+{
+	/* Instruction opcode for TILERELEASE; supported in binutils >= 2.36. */
+	asm volatile(".byte 0xc4, 0xe2, 0x78, 0x49, 0xc0");
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_X86_SPECIAL_INSNS_H */
diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c
index cccfeafe81e5..14c8216d9a39 100644
--- a/arch/x86/kernel/fpu/core.c
+++ b/arch/x86/kernel/fpu/core.c
@@ -106,6 +106,17 @@ int copy_fpregs_to_fpstate(struct fpu *fpu)
 		 */
 		if (fpu->state->xsave.header.xfeatures & XFEATURE_MASK_AVX512)
 			fpu->avx512_timestamp = jiffies;
+
+		/*
+		 * Leaving state in the TILE registers may prevent the
+		 * processor from entering low-power idle states. Use
+		 * TILERELEASE to initialize the state. Destroying
+		 * fpregs state is safe after the fpstate update.
+		 */
+		if (fpu->state_mask & XFEATURE_MASK_XTILE_DATA) {
+			tile_release();
+			fpregs_deactivate(fpu);
+		}
 		return 1;
 	}
 
-- 
2.17.1