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From:   Ard Biesheuvel <ardb@kernel.org>
Date:   Wed, 26 May 2021 16:15:01 +0200
Message-ID: <CAMj1kXGBEuV=OUeCWUj5iUbFmko549uKCt5eHFM_j2KW-_FNdw@mail.gmail.com>
Subject: Re: [BUG] rockpro64: PCI BAR reassignment broken by commit
 9d57e61bf723 ("of/pci: Add IORESOURCE_MEM_64 to resource flags for 64-bit
 memory addresses")
To:     =?UTF-8?Q?Christian_K=C3=B6nig?= <ckoenig.leichtzumerken@gmail.com>
Cc:     Peter Geis <pgwipeout@gmail.com>,
        Punit Agrawal <punitagrawal@gmail.com>,
        Robin Murphy <robin.murphy@arm.com>,
        Alexandru Elisei <alexandru.elisei@arm.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        arm-mail-list <linux-arm-kernel@lists.infradead.org>,
        Heiko Stuebner <heiko.stuebner@theobroma-systems.com>,
        Leonardo Bras <leobras.c@gmail.com>,
        Rob Herring <robh@kernel.org>, PCI <linux-pci@vger.kernel.org>
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On Wed, 26 May 2021 at 15:55, Christian K=C3=B6nig
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Hi Ard,
>
> Am 25.05.21 um 19:18 schrieb Ard Biesheuvel:
> > [SNIP]
> >>> I seriously doubt that this is what is going on here.
> >>>
> >>> lspci -x will give you the bare BAR values - I suspect that those are
> >>> probably fine.
> >> lspci -x
> >> 00:00.0 PCI bridge: Fuzhou Rockchip Electronics Co., Ltd Device 3566 (=
rev 01)
> >> 00: 87 1d 66 35 07 05 10 40 01 00 04 06 00 00 01 00
> >> 10: 00 00 00 00 00 00 00 00 00 01 ff 00 10 10 00 20
> >> 20: 00 10 00 10 01 00 f1 0f 00 00 00 00 00 00 00 00
> >> 30: 00 00 00 00 40 00 00 00 00 00 00 00 5f 01 02 00
> >>
> >> 01:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
> >> [AMD/ATI] Turks PRO [Radeon HD 7570]
> >> 00: 02 10 5d 67 07 00 10 20 00 00 00 03 00 00 80 00
> >> 10: 0c 00 00 00 00 00 00 00
> > This is a 64-bit prefetchable BAR programmed with bus address 0x0
> >
> >> 04 00 00 10 00 00 00 00
> > This is a 64-bit non-prefetchable BAR programmed with bus address 0x100=
0_0000
> >
> > (https://en.wikipedia.org/wiki/PCI_configuration_space describes the
> > meaning of the low order BAR bits)
>
> Sorry for jumping into the middle of the discussion and to be honest I
> haven't fully read it.
>
> This looks a bit odd since on AMD VGA hardware the non-prefetchable BAR
> is usually only 32bit, not 64bit.
>
> But this hardware generation is rather old and I'm not sure what the BAR
> assignment for that generation was. I would need to dig up the register
> description in our archives as well.
>

I have another museum piece in my AMD Seattle:

02:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
[AMD/ATI] Oland XT [Radeon HD 8670 / R7 250/350] (rev 81) (prog-if 00
[VGA controller])
  Subsystem: Dell Oland XT [Radeon HD 8670 / R7 250/350]
  Flags: bus master, fast devsel, latency 0, IRQ 255
  Memory at 100000000 (64-bit, prefetchable) [size=3D4G]
  Memory at 40000000 (64-bit, non-prefetchable) [size=3D256K]
  I/O ports at 1000 [disabled] [size=3D256]
  Expansion ROM at 40060000 [disabled] [size=3D128K]
  Capabilities: <access denied>
  Kernel modules: radeon, amdgpu

So AMD/ATI ASICs definitely exist that expose a 64-bit pref and a
64-bit non-pref BAR.

--=20
Ard.