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Date:   Wed, 26 May 2021 14:54:01 +0000
From:   Sean Christopherson <seanjc@google.com>
To:     "Liu, Jing2" <jing2.liu@linux.intel.com>
Cc:     pbonzini@redhat.com, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org, jing2.liu@intel.com
Subject: Re: [PATCH RFC 7/7] kvm: x86: AMX XCR0 support for guest
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References: <20210207154256.52850-1-jing2.liu@linux.intel.com>
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 <43eb3317-4101-0786-57f4-f35e7ec094eb@linux.intel.com>
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On Wed, May 26, 2021, Liu, Jing2 wrote:
> 
> On 5/25/2021 5:53 AM, Sean Christopherson wrote:
> > On Sun, Feb 07, 2021, Jing Liu wrote:
> > > Two XCR0 bits are defined for AMX to support XSAVE mechanism.
> > > Bit 17 is for tilecfg and bit 18 is for tiledata.
> > This fails to explain why they must be set in tandem.
> The spec says, "executing the XSETBV instruction causes a general-protection
> fault (#GP) if ECX=0 and EAX[17] ≠ EAX[18] (XTILECFG and XTILEDATA must be
> enabled together).  This implies that the value of XCR0[17:18] is always
> either 00b or 11b."
> 
> I can add more to changelog if this is reasonable.

Ya, please do.  It doesn't have to be the full thing verbatim (but that's ok, too),
but the requirement does need to be called out.

> >  Out of curisoity, assuming they do indeed need to be set/cleared as a
> >  pair, what's the point of having two separate bits?
>
> What I can see is to separate different states and mirror by XFD which can
> set bits separately.

Ah, that would make sense.  Thanks!