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[23.128.96.18]) by mx.google.com with ESMTP id w12si904119jad.49.2021.05.26.18.05.04; Wed, 26 May 2021 18:05:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RFpfi51X; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234589AbhEZWsa (ORCPT + 99 others); Wed, 26 May 2021 18:48:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234099AbhEZWs3 (ORCPT ); Wed, 26 May 2021 18:48:29 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13B36C06175F for ; Wed, 26 May 2021 15:46:56 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id a5so4253731lfm.0 for ; Wed, 26 May 2021 15:46:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Gh6D0NmIuyBi9REXwAXFztqizN+UX22Sn24ASBHof08=; b=RFpfi51XYUTh4MvV3R5Rf5owzqAC2vrcks9E7IOUfBd9gRw34msYfBl503zc5r/YHg 9u4wCA+i9E1Lx6FfC/a7m02x0mzD/fvkTN1Z9ZxFsnBZq+kiWoqrjVKOS95NgDJKjAya ISaFVPtioEikoHd+xVWcLLpsGJUGmJUoThYY5dlqM24dRpef7Pz2D3naNbhSeC2jOeWw VdwSg8PyXurJHDyhzkgVNnXC+sWJIPokokEhAFa9qwsqu+fqK/K8d58fNgMX+a/nn6p3 RXfzf5aZXdPgH8cKAQJ+dBdlajGQ/EEyIg3phuR/vUAL2+7vfQd8C9INrFjCOjl9dCq0 Vw8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Gh6D0NmIuyBi9REXwAXFztqizN+UX22Sn24ASBHof08=; b=kPEiKiEw0bEPKJRuZpJnUrU6JYN7QBowhibE+MXQwu0+9H3g9hrpsC2GX7Rk7B2tTj tCscgSHjiST95Ig2KlSSEsmRRCw6wBS7EwZlq0f5WK8ZpHKidq+kOrVjRZv8rGzNlKq7 j1XWo1cJFbLIfZM4KXJ0L/yoK2N02Wo3H+hV6nlpyXMV/o30wr+GSdtkWxZq4TqYPUIT yaAAGrDrtrPbRn9rBRtROZGxjWaUG46Sdq4KLLFvNjKGqFVh93OYJRkysKs2G5Aguas4 vMbLEIFCGcZn0rm8V3WQvYIyt8AmEUqAJWzalHhOTza0WpkZxsfKKBLs8i2ZFoo+5avj d3LA== X-Gm-Message-State: AOAM531DM4kI0WeWiMqMOS4wVSf/y4mVSVOr6ifwKMJzaX8skr+igEUt EppeDXlLItWGfMi5iB4VLnKu7RxDDyxs5e585+wnGQ== X-Received: by 2002:a05:6512:11ea:: with SMTP id p10mr237601lfs.157.1622069214022; Wed, 26 May 2021 15:46:54 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Linus Walleij Date: Thu, 27 May 2021 00:46:42 +0200 Message-ID: Subject: Re: [PATCH v4 0/3] gpio: gpio-regmap: Support few custom operations To: Matti Vaittinen Cc: Matti Vaittinen , Bartosz Golaszewski , Michael Walle , Florian Fainelli , bcm-kernel-feedback-list , Jonas Gorski , =?UTF-8?B?w4FsdmFybyBGZXJuw6FuZGV6IFJvamFz?= , "open list:GPIO SUBSYSTEM" , linux-kernel , linux-power@fi.rohmeurope.com, Linux ARM , Andy Shevchenko Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 26, 2021 at 8:02 AM Matti Vaittinen wrote: > Support providing some IC specific operations at gpio_regmap registration. I see there is some discussion around the abstractions here. I can only say how we designed gpio-mmio.c (CONFIG_GPIO_GENERIC). It was designed for GPIO controllers with 8, 16 or 32 bits of GPIO, each stuffed in a consecutive bit in a set of registers. We later amended it to deal with bigendian as well, and 64 bit registers, and some quirks around the registers (like just readable etc). But that's it. For anything more complex we have opted for users to write their own drivers with elaborate code. As library it can sometimes be combined with an irqchip, if the interrupts are simple. But overall: each GPIO needs to be a single bit, not 2 not 3 not in every 7th register etc. I would not try to turn gpio regmap into a Rube Goldberg Machine panacea-fit-all for all kinds of register and bit layouts, it's nice to be able to combine it with an interrupt chip or pin controller if those functions are also simple, like the set/get registers. Any too bold ambitions will be hard to maintain, I think. Yours, Linus Walleij