Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp328381pxj; Thu, 27 May 2021 00:46:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKsg9JR4Fntiq2b97OJxjpFYaNJUfIuLkq2j+DZCKyKvrHDAhGPYcmgukZKfLgeC6zHB8R X-Received: by 2002:a02:5289:: with SMTP id d131mr2255887jab.121.1622101597634; Thu, 27 May 2021 00:46:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622101597; cv=none; d=google.com; s=arc-20160816; b=nJo8wjFB8uPwXAKcQuRtPBMzXxy11JVKq57onYG0wDJKe5fK34UhqVWC8h1ZQ5eUt5 e/yRup4pX1oqTD1rU6p/P2FdGrCnDIxNvRdQr11yrzK3Qt4w22fV3KYThKr2s9IGo0Gl 8QgSIf0vXU2dp/0EYlYq8+NWgfD9h2rTP3uGemXuM9gbg6SoGLAjW3H25eieokowfkOU Yzt16gH05KFDRv/MPq7KywaP+nULzT/equ+6BfsUOi5CbY8IjqRFnUbw1oJfOFd1FNjR rFfM98/TlziEVYhBoC0OrH+FOKSoKu3uGLCviao9xrKBxZCZgezN6hHhoWABBH1OEtCb BzZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=cSBg+pRfv6S+Nvgs9JSzH+qnRV8JAEOAAuVhhuH96rI=; b=w3ajYgB1Jx5QEIp3xGptM+E35b+0akPsL0yklROzvY5+RIdyHcSlYAVNFga94fcWPQ uOPRyRxciBSsArnpJZ/lleqkHogf20SBdYaGFMVa4wDCa1RbPySX/1/xWqX/acfEN4t4 YMDh5nOLgqnrvg2vUDHVhD4C73uPi3H+pdcOBGAvyNACtcAQ5Jo3JOwx2mQ7JdTorEW8 sGoFw+aKdMt343aVwnAnIWZVoWCTWHVw5wTjpNI1QMLGvcvzUDQYtImSTsB7Q9sU5IKk 7bMKkxZtMNisnPxnLYnqHXYv2fU+hHUN5z2DLCIpCSXcp3rtlUjaBFpj0IPLws9J1Xkp fDjg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y7si2045898jap.36.2021.05.27.00.46.23; Thu, 27 May 2021 00:46:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234779AbhE0Ha4 (ORCPT + 99 others); Thu, 27 May 2021 03:30:56 -0400 Received: from lucky1.263xmail.com ([211.157.147.135]:41102 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234635AbhE0Haz (ORCPT ); Thu, 27 May 2021 03:30:55 -0400 Received: from localhost (unknown [192.168.167.235]) by lucky1.263xmail.com (Postfix) with ESMTP id 32853AC981; Thu, 27 May 2021 15:29:21 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P31748T140095032067840S1622100559925996_; Thu, 27 May 2021 15:29:21 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-RCPT-COUNT: 6 X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, lee.jones@linaro.org, ulf.hansson@linaro.org Cc: linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jianqun Xu Subject: [PATCH] soc: rockchip: io-domain: add rk3568 support Date: Thu, 27 May 2021 15:29:17 +0800 Message-Id: <20210527072917.1425321-1-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The io-domain registers on RK3568 SoCs have three separated bits to enable/disable the 1.8v/2.5v/3.3v power. This patch make the write to be a operation, allow rk3568 uses a private register set function. Since the 2.5v is not used on RK3568, so the driver only set 1.8v [enable] + 3.3v [disable] for 1.8v mode 1.8v [disable] + 3.3v [enable] for 3.3v mode There is not register order requirement which has been cleared by our IC team. Signed-off-by: Jianqun Xu --- drivers/soc/rockchip/io-domain.c | 75 +++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c index cf8182fc3642..32b3bd645d56 100644 --- a/drivers/soc/rockchip/io-domain.c +++ b/drivers/soc/rockchip/io-domain.c @@ -51,6 +51,10 @@ #define RK3399_PMUGRF_CON0_VSEL BIT(8) #define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9 +#define RK3568_PMU_GRF_IO_VSEL0 (0x0140) +#define RK3568_PMU_GRF_IO_VSEL1 (0x0144) +#define RK3568_PMU_GRF_IO_VSEL2 (0x0148) + struct rockchip_iodomain; struct rockchip_iodomain_soc_data { @@ -71,8 +75,51 @@ struct rockchip_iodomain { struct regmap *grf; const struct rockchip_iodomain_soc_data *soc_data; struct rockchip_iodomain_supply supplies[MAX_SUPPLIES]; + int (*write)(struct rockchip_iodomain_supply *supply, int uV); }; +static int rk3568_pmu_iodomain_write(struct rockchip_iodomain_supply *supply, + int uV) +{ + struct rockchip_iodomain *iod = supply->iod; + u32 is_3v3 = uV > MAX_VOLTAGE_1_8; + u32 val0, val1; + int b; + + switch (supply->idx) { + case 0: /* pmuio1 */ + break; + case 1: /* pmuio2 */ + b = supply->idx; + val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); + b = supply->idx + 4; + val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0); + + regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val0); + regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val1); + break; + case 3: /* vccio2 */ + break; + case 2: /* vccio1 */ + case 4: /* vccio3 */ + case 5: /* vccio4 */ + case 6: /* vccio5 */ + case 7: /* vccio6 */ + case 8: /* vccio7 */ + b = supply->idx - 1; + val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); + val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0); + + regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL0, val0); + regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL1, val1); + break; + default: + return -EINVAL; + }; + + return 0; +} + static int rockchip_iodomain_write(struct rockchip_iodomain_supply *supply, int uV) { @@ -136,7 +183,7 @@ static int rockchip_iodomain_notify(struct notifier_block *nb, return NOTIFY_BAD; } - ret = rockchip_iodomain_write(supply, uV); + ret = supply->iod->write(supply, uV); if (ret && event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE) return NOTIFY_BAD; @@ -398,6 +445,21 @@ static const struct rockchip_iodomain_soc_data soc_data_rk3399_pmu = { .init = rk3399_pmu_iodomain_init, }; +static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = { + .grf_offset = 0x140, + .supply_names = { + "pmuio1", + "pmuio2", + "vccio1", + "vccio2", + "vccio3", + "vccio4", + "vccio5", + "vccio6", + "vccio7", + }, +}; + static const struct rockchip_iodomain_soc_data soc_data_rv1108 = { .grf_offset = 0x404, .supply_names = { @@ -469,6 +531,10 @@ static const struct of_device_id rockchip_iodomain_match[] = { .compatible = "rockchip,rk3399-pmu-io-voltage-domain", .data = &soc_data_rk3399_pmu }, + { + .compatible = "rockchip,rk3568-pmu-io-voltage-domain", + .data = &soc_data_rk3568_pmu + }, { .compatible = "rockchip,rv1108-io-voltage-domain", .data = &soc_data_rv1108 @@ -502,6 +568,11 @@ static int rockchip_iodomain_probe(struct platform_device *pdev) match = of_match_node(rockchip_iodomain_match, np); iod->soc_data = match->data; + if (match->data == &soc_data_rk3568_pmu) + iod->write = rk3568_pmu_iodomain_write; + else + iod->write = rockchip_iodomain_write; + parent = pdev->dev.parent; if (parent && parent->of_node) { iod->grf = syscon_node_to_regmap(parent->of_node); @@ -562,7 +633,7 @@ static int rockchip_iodomain_probe(struct platform_device *pdev) supply->reg = reg; supply->nb.notifier_call = rockchip_iodomain_notify; - ret = rockchip_iodomain_write(supply, uV); + ret = iod->write(supply, uV); if (ret) { supply->reg = NULL; goto unreg_notify; -- 2.25.1