Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp333086pxj; Thu, 27 May 2021 00:56:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzfauzawK1UITpOTdjcX7MIbvFu4cT0TJ2/0Iy+CzbaRaOg0FJuFsDJgNsO46GVXx6CP0OG X-Received: by 2002:a6b:7948:: with SMTP id j8mr1829661iop.32.1622102204071; Thu, 27 May 2021 00:56:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622102204; cv=none; d=google.com; s=arc-20160816; b=s3RI8vNpiXbkXkNCT/+FXPN4RC9eN3AP878ZKwYeVr/QVasUxA7WjvpnQvk6Hkt9tw xqNdepzHJIiDZcTEqKzCI6+nQxbXZQi7Ac/dWAS/ykOPRVtiI0PrsZIve4nUtK0uAn/x QaU/roxYv+371KeaYu2rG6M6Q4dpVy5OjPyIHMikKfo5cGiNJs5x6a0aj8gkQQ+ioFxF mDsexj+nwN7Mb3knfasg7nbe56GWw++e0j7Hw9Pj/j4yhlt0KvZwHp7tq1x2/EdVc5mr WnfJKKx7r+GsLqpBRhIKXFh50qfhDhqgKy04F63WQx850EpaZwK2DGw5P2OH374eiTpS n6TA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:ironport-sdr:ironport-sdr; bh=CSX6AYwajPPeSFOxBoIitv+ir89mzyWLJqdRlddP9aI=; b=T/rcVD1feeyWQLQCblUaGeCozJ/Zv8wAmRXi11E/2NlwE/fWK/ZRbeZe6vQX89ksCY C350hUVgR/jDyI9viRld3oNE/aRJ/FlNj2rgwK2n7C82j8b4iwFyCJPtsul4Z2Bv3mUY NSmjSU9Ojug7kIC8ykDNf2nX8GbKOCplW6moVoW+o+CYPUbW5lEf1bHJFLEIDGAZQpju sVdEPX0ecBY3LnH6L3liJrUWX30eI3iDqUvGoTJf3C4wQvR+VSFIYwRq/N+0SZUwmfuC gbKWzK2jXRHPqNqm+Gfpq/X9dMWoK1JBpgUWhEei/pCm9FsBNgJWwmklEJpx8/ar9s97 7jGA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y7si2045898jap.36.2021.05.27.00.56.30; Thu, 27 May 2021 00:56:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234865AbhE0H4M (ORCPT + 99 others); Thu, 27 May 2021 03:56:12 -0400 Received: from mga05.intel.com ([192.55.52.43]:39405 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234785AbhE0H4K (ORCPT ); Thu, 27 May 2021 03:56:10 -0400 IronPort-SDR: s7e0hZ733MloFJrRFAzm6yJRmVX2oQdhsWd/JDAxnIWf23/02IV81ol2AJauDgcBIf5ezhCF+X TB7eidTqeZTg== X-IronPort-AV: E=McAfee;i="6200,9189,9996"; a="288262817" X-IronPort-AV: E=Sophos;i="5.82,334,1613462400"; d="scan'208";a="288262817" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2021 00:54:34 -0700 IronPort-SDR: b6NHUZEPTxBCG2Pthb8OR2kJ9TJjq7ZfoiPZBJbXuoUaLtVniYnCxkurQrlStnSs3vfJTCf4CC 3AXz1+QbijRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,334,1613462400"; d="scan'208";a="547586505" Received: from kbl-ppc.sh.intel.com ([10.239.159.163]) by fmsmga001.fm.intel.com with ESMTP; 27 May 2021 00:54:32 -0700 From: Jin Yao To: acme@kernel.org, jolsa@kernel.org, peterz@infradead.org, mingo@redhat.com, alexander.shishkin@linux.intel.com Cc: Linux-kernel@vger.kernel.org, ak@linux.intel.com, kan.liang@intel.com, yao.jin@intel.com, Jin Yao Subject: [PATCH v2 1/8] perf tools: Check mem-loads auxiliary event Date: Thu, 27 May 2021 08:16:03 +0800 Message-Id: <20210527001610.10553-2-yao.jin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210527001610.10553-1-yao.jin@linux.intel.com> References: <20210527001610.10553-1-yao.jin@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For some platforms, an auxiliary event has to be enabled simultaneously with the load latency event. For Alderlake, the auxiliary event is created in "cpu_core" pmu. So first we need to check the existing of "cpu_core" pmu and then check if this pmu has auxiliary event. Signed-off-by: Jin Yao --- v2: - No change. tools/perf/arch/x86/util/mem-events.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tools/perf/arch/x86/util/mem-events.c b/tools/perf/arch/x86/util/mem-events.c index 588110fd8904..e79232e3f2a0 100644 --- a/tools/perf/arch/x86/util/mem-events.c +++ b/tools/perf/arch/x86/util/mem-events.c @@ -11,8 +11,13 @@ static bool mem_loads_name__init; bool is_mem_loads_aux_event(struct evsel *leader) { - if (!pmu_have_event("cpu", "mem-loads-aux")) - return false; + if (perf_pmu__find("cpu")) { + if (!pmu_have_event("cpu", "mem-loads-aux")) + return false; + } else if (perf_pmu__find("cpu_core")) { + if (!pmu_have_event("cpu_core", "mem-loads-aux")) + return false; + } return leader->core.attr.config == MEM_LOADS_AUX; } -- 2.17.1