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Thu, 27 May 2021 11:53:10 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 27 May 2021 04:53:09 -0700 Received: from buildserver-hdc-comms.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 27 May 2021 04:53:06 -0700 From: Om Prakash Singh To: , , , , CC: , , , , , Om Prakash Singh Subject: [RESEND PATCH V1 4/5] PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode Date: Thu, 27 May 2021 17:22:45 +0530 Message-ID: <20210527115246.20509-5-omp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210527115246.20509-1-omp@nvidia.com> References: <20210527115246.20509-1-omp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b8c38a60-a37d-4b12-2f36-08d92105ffed X-MS-TrafficTypeDiagnostic: BN6PR1201MB2531: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4502; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2021 11:53:10.0833 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8c38a60-a37d-4b12-2f36-08d92105ffed X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB2531 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When Tegra PCIe is in endpoint mode it should be available for root port. PCIe link up by root port fails if it is in suspend state. So, don't allow Tegra to suspend when endpoint mode is enabled. Signed-off-by: Om Prakash Singh --- drivers/pci/controller/dwc/pcie-tegra194.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index ae62fdc840e6..93c89f2084a7 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2276,6 +2276,11 @@ static int tegra_pcie_dw_suspend_late(struct device *dev) struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); u32 val; + if (pcie->mode == DW_PCIE_EP_TYPE) { + dev_err(dev, "Tegra PCIe is in EP mode, suspend not allowed"); + return -EPERM; + } + if (!pcie->link_state) return 0; -- 2.17.1