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Bae" , Borislav Petkov , Thomas Gleixner , Ingo Molnar , X86 ML , "Brown, Len" , "Liu, Jing2" , "Ravi V. Shankar" , Linux Kernel Mailing List , "Chen, Tim C" Subject: Re: [PATCH v5 28/28] x86/fpu/amx: Clear the AMX state when appropriate Message-ID: References: <20210523193259.26200-1-chang.seok.bae@intel.com> <20210523193259.26200-29-chang.seok.bae@intel.com> <1980c78b-d51b-c186-9179-f3c72692ad8a@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 24, 2021 at 02:24:54PM -0400, Len Brown wrote: > On Mon, May 24, 2021 at 1:39 PM Dave Hansen wrote: > > > >> might be considered nasty. > > > > I'm not excited about burdening the generic idle path with a CPU > > > feature specific check that would need to be checked on every idle > > > entry. > > > > Me neither. > > > > But, the check itself should be cheap. A cpu_feature_enabled(AMX) check > > will eliminate even the cost of a branch on systems without AMX. You > > could probably even get fancy and also use a static branch that doesn't > > get enabled until the first AMX user shows up. > > It isn't just the hardware run-time cost. > It is the source code complexity. > That code is 100% generic. Why can't this live in intel_idle.c ? We had to pull out CPUIDLE_FLAG_TLB_FLUSH because leave_mm() requires RCU, but afaict both TILERELEASE and XRESTOR do not and could be added to intel_idle_tile(), which can be used in XXX_cstates[] for the relevant chips instead of intel_idle() for C6 and up. intel_idle_tile(args) { bool has_tile = // something XINUSE if (has_tile) TILERELEASE intel_idle(args...); if (has_tile) // something XRESTOR } Hmm?