Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp19859pxj; Thu, 27 May 2021 19:59:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwAfqZgw+TdnEi5jf69fhk/07d51GQ+O5P4dQx19x/uycgbMNbMo3Dxq5AX2PPUXN70lMex X-Received: by 2002:a5d:9acd:: with SMTP id x13mr5243938ion.134.1622170745317; Thu, 27 May 2021 19:59:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622170745; cv=none; d=google.com; s=arc-20160816; b=1IQD+tQBdsXNRRgyQa+1qvujziKrYA7GMx0gYWtfSd8IV56Gs78gLhiRTJbedrkqyA 5uETNB5Yd+usOd+eLOc5Q9qEBTz7Hoy4dmEO915Maw58CmNb+Hvwq2KgoOJbOz1YNOXQ B10ZAV61b9d2gUIftD5/17X0B2jYuhl8pMuIWsBtVU3eoYYxr19m32K1KY+9An+WuNfs TfscUMsCwLLwnQ/CQOV/bTws5NydbOLT8JNZFirrBeg7klyAjG10HYQHDNAKIiUaCshA KxFZ7IVJLT4EWAPyEJ2d8EqjAxIVNQ7JtzESBstHfBvRy56QmA12H1GJ4f5KIDBKBV6j bycQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=b7vUSPsMjmRSHQnk6PDdtebfR3rhaE5+nKWdNkzbU9U=; b=IYLSrbObxQiFhxECV8pjfQfBrKe8v/VO4iz0r9ZwO3TfEGfCVn3Vm/7v0zOX0G268l e7EuORjJMncY+gv/36KfgUOb6Tg1b0m1S9ciA9fNc3BbZhJqLfk5Am/46YR2+8j/zdM5 LTrr4VW5i5hRzldEg/Op8wb0N50RnqqDtbYveNO9E6P0Aj/A1i1Jpq5VCOSmk7kKSu9D v3KobD275tN6VacAZehsJ2xyX8ZvjT4HzPkmmXtfYlyYzE6bgHoLO+feuCmnM02j+Ktd i6eSXYGlDESmSoGMjeCr7R4PZOoQtDX8BiL0KUPZa9iIzbewd2AQUIAXuKIWfoEJ7psx N7NA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t188si3790356jaa.52.2021.05.27.19.58.49; Thu, 27 May 2021 19:59:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=crapouillou.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236750AbhE0XXe (ORCPT + 99 others); Thu, 27 May 2021 19:23:34 -0400 Received: from aposti.net ([89.234.176.197]:36112 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236723AbhE0XXb (ORCPT ); Thu, 27 May 2021 19:23:31 -0400 From: Paul Cercueil To: David Airlie , Daniel Vetter , Thomas Zimmermann , Maxime Ripard Cc: list@opendingux.net, linux-mips@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Neil Armstrong , Paul Cercueil Subject: [PATCH 06/11] drm/ingenic: Set DMA descriptor chain register when starting CRTC Date: Fri, 28 May 2021 00:21:00 +0100 Message-Id: <20210527232104.152577-7-paul@crapouillou.net> In-Reply-To: <20210527232104.152577-1-paul@crapouillou.net> References: <20210527232104.152577-1-paul@crapouillou.net> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Setting the DMA descriptor chain register in the probe function has been fine until now, because we only ever had one descriptor per foreground. As the driver will soon have real descriptor chains, and the DMA descriptor chain register updates itself to point to the current descriptor being processed, this register needs to be reset after a full modeset to point to the first descriptor of the chain. Signed-off-by: Paul Cercueil --- drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index 639994329c60..5ba3283da97d 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -210,6 +210,10 @@ static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, regmap_write(priv->map, JZ_REG_LCD_STATE, 0); + /* Set address of our DMA descriptor chain */ + regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_addr(priv, 0)); + regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_addr(priv, 1)); + regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_ENABLE); @@ -1218,10 +1222,6 @@ static int ingenic_drm_bind(struct device *dev, bool has_components) } } - /* Set address of our DMA descriptor chain */ - regmap_write(priv->map, JZ_REG_LCD_DA0, dma_hwdesc_phys_f0); - regmap_write(priv->map, JZ_REG_LCD_DA1, dma_hwdesc_phys_f1); - /* Enable OSD if available */ if (soc_info->has_osd) regmap_write(priv->map, JZ_REG_LCD_OSDC, JZ_LCD_OSDC_OSDEN); -- 2.30.2