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(72-28-179-94.pool.ukrtel.net. [94.179.28.72]) by smtp.gmail.com with ESMTPSA id a12sm655820ljk.34.2021.05.28.13.31.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 May 2021 13:31:04 -0700 (PDT) From: Roman Stratiienko To: linux-kernel@vger.kernel.org Cc: mripard@kernel.org, wens@csie.org, jernej.skrabec@siol.net, megous@megous.com, linux-sunxi@googlegroups.com, dri-devel@lists.freedesktop.org, Roman Stratiienko Subject: [PATCH v4 2/2] drm/sun4i: Use CRTC size instead of primary plane size as mixer frame Date: Fri, 28 May 2021 23:30:36 +0300 Message-Id: <20210528203036.17999-3-r.stratiienko@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210528203036.17999-1-r.stratiienko@gmail.com> References: <20210528203036.17999-1-r.stratiienko@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fixes corrupted display picture when primary plane isn't full-screen. Signed-off-by: Roman Stratiienko --- drivers/gpu/drm/sun4i/sun8i_mixer.c | 28 ++++++++++++++++++++++++ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 30 -------------------------- 2 files changed, 28 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index 5b42cf25cc86..810c731566c0 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -248,6 +248,33 @@ int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format) return -EINVAL; } +static void sun8i_mode_set(struct sunxi_engine *engine, + struct drm_display_mode *mode) +{ + u32 size = SUN8I_MIXER_SIZE(mode->crtc_hdisplay, mode->crtc_vdisplay); + struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); + u32 bld_base = sun8i_blender_base(mixer); + u32 val; + + DRM_DEBUG_DRIVER("Mode change, updating global size W: %u H: %u\n", + mode->crtc_hdisplay, mode->crtc_vdisplay); + regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_SIZE, size); + regmap_write(mixer->engine.regs, + SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; + else + val = 0; + + regmap_update_bits(mixer->engine.regs, + SUN8I_MIXER_BLEND_OUTCTL(bld_base), + SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, + val); + DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", + val ? "on" : "off"); +} + static void sun8i_mixer_commit(struct sunxi_engine *engine) { DRM_DEBUG_DRIVER("Committing changes\n"); @@ -301,6 +328,7 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm, static const struct sunxi_engine_ops sun8i_engine_ops = { .commit = sun8i_mixer_commit, .layers_init = sun8i_layers_init, + .mode_set = sun8i_mode_set, }; static const struct regmap_config sun8i_mixer_regmap_config = { diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index 0db164a774a1..d66fff582278 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -120,36 +120,6 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, insize = SUN8I_MIXER_SIZE(src_w, src_h); outsize = SUN8I_MIXER_SIZE(dst_w, dst_h); - if (plane->type == DRM_PLANE_TYPE_PRIMARY) { - bool interlaced = false; - u32 val; - - DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n", - dst_w, dst_h); - regmap_write(mixer->engine.regs, - SUN8I_MIXER_GLOBAL_SIZE, - outsize); - regmap_write(mixer->engine.regs, - SUN8I_MIXER_BLEND_OUTSIZE(bld_base), outsize); - - if (state->crtc) - interlaced = state->crtc->state->adjusted_mode.flags - & DRM_MODE_FLAG_INTERLACE; - - if (interlaced) - val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; - else - val = 0; - - regmap_update_bits(mixer->engine.regs, - SUN8I_MIXER_BLEND_OUTCTL(bld_base), - SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, - val); - - DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", - interlaced ? "on" : "off"); - } - /* Set height and width */ DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n", state->src.x1 >> 16, state->src.y1 >> 16); -- 2.30.2