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Sun, 30 May 2021 08:35:59 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 30 May 2021 08:35:59 +0000 Received: from vdi.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 30 May 2021 08:35:57 +0000 From: Eli Cohen To: , , , CC: Subject: [PATCH v1] vdpa/mlx5: Fix umem sizes assignments on VQ create Date: Sun, 30 May 2021 11:35:48 +0300 Message-ID: <20210530083548.6545-1-elic@nvidia.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e38ebf6d-e894-4841-9cad-08d92345f3a7 X-MS-TrafficTypeDiagnostic: BN6PR1201MB0100: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:556; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: g8lwX0jp9ehgq2fTwrcs8tGLdeE9tm8odGrXn1CTPZPF8hUxuSAAKTEIvHm5Yk0suOmvT17SNaZ+6V7JWOOPmwEJ92AcNMVu17f0uFo/u+taptH+Vtv7XQWujUc+ZsCwkexbNXuaeRofvxoH/9QhI/Ihc5dgy8sCDFjyILEDVrclyMS31iHkaPcKybTwPp3dekw+oTY7O3IVRcDAkPvE7l8jKK9Uz9r0kvYRcX66K5Kv90FrAy03mBNJLD5KpntXrJmQgrM6nCZEsLirBi9nJVykyGplunlD8B7v54CCzC7iChX1JDnoPDySkrbvw9cuFBTGd+2BiAG3HiY1jwwoOeI1MFe5RBYjLfAfEUDJDICERUWoDUoL7fchoHfaQPUg5LfgG+xYZTpqDo2D1C4hoRyAfNKVv7N4CwVXJ3kJlCBRIcuyJTJw9obYgtN0jMIR4BvfPdLxyENg1aSl2iof1S5mnlgKSiElegEOsnkvc0o1oVEVIVRzY3A1YqeBzH7ZuXuyex/SH74gfjL5iHIV2V/5P8kS2adH6IPL2oLWo5BUpLKC2Bxw9whKTExevYXpFnDEd+FYisy3ePQfNXup101VyzXmN0Hpd+Ixlj0SDcFp4736kvn5OiLubn3fYTvHD65u+mdn2VRg6WZGKYjvFeIlQVULID1jZhHlUKWCW4Y= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(396003)(346002)(376002)(136003)(39860400002)(46966006)(36840700001)(47076005)(186003)(2906002)(36860700001)(70206006)(26005)(70586007)(4326008)(82740400003)(86362001)(336012)(82310400003)(7636003)(5660300002)(36756003)(356005)(2616005)(1076003)(7696005)(8936002)(107886003)(110136005)(478600001)(6666004)(8676002)(316002)(83380400001)(426003)(36906005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 May 2021 08:35:59.6210 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e38ebf6d-e894-4841-9cad-08d92345f3a7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0100 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix copy paste bug assigning umem1 size to umem2 and umem3. The issue was discovered when trying to use a 1:1 MR that covers the entire address space where firmware complained that provided sizes are not large enough. 1:1 MRs are requied to support virtio_vdpa. Fixes: 1a86b377aa21 ("vdpa/mlx5: Add VDPA driver for supported mlx5 devices") Signed-off-by: Eli Cohen --- V0 --> V1: Add more information in changelog drivers/vdpa/mlx5/net/mlx5_vnet.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 189e4385df40..53312f0460ad 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -828,9 +828,9 @@ static int create_virtqueue(struct mlx5_vdpa_net *ndev, struct mlx5_vdpa_virtque MLX5_SET(virtio_q, vq_ctx, umem_1_id, mvq->umem1.id); MLX5_SET(virtio_q, vq_ctx, umem_1_size, mvq->umem1.size); MLX5_SET(virtio_q, vq_ctx, umem_2_id, mvq->umem2.id); - MLX5_SET(virtio_q, vq_ctx, umem_2_size, mvq->umem1.size); + MLX5_SET(virtio_q, vq_ctx, umem_2_size, mvq->umem2.size); MLX5_SET(virtio_q, vq_ctx, umem_3_id, mvq->umem3.id); - MLX5_SET(virtio_q, vq_ctx, umem_3_size, mvq->umem1.size); + MLX5_SET(virtio_q, vq_ctx, umem_3_size, mvq->umem3.size); MLX5_SET(virtio_q, vq_ctx, pd, ndev->mvdev.res.pdn); if (MLX5_CAP_DEV_VDPA_EMULATION(ndev->mvdev.mdev, eth_frame_offload_type)) MLX5_SET(virtio_q, vq_ctx, virtio_version_1_0, 1); -- 2.31.1