Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp1809434pxj; Sun, 30 May 2021 04:10:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxQ7F2SMm6g+UFNbqiY18VkiKTA9Cqr/Dbcot7urYLdoANzte4hE0qcjXyhHCcz3FLuQbXC X-Received: by 2002:a17:906:6ad0:: with SMTP id q16mr18461633ejs.286.1622373025663; Sun, 30 May 2021 04:10:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622373025; cv=none; d=google.com; s=arc-20160816; b=YXjoAWREYD0noWZKQ+nweqXJPIePHT4hbxsIBffNfOvs2gC05cTMlUzo+VqqFkTPEf c10UX/V8SQnxDoGVytyyaC9zCm5n7Cc4Uh7JRB8Sv+irJgdVGimc0K1lBFK9Ciiya8JI g5bE99foFuGiBjlX5BsoX6NNqHRc+peFX34ATH0tp0RKXdbLbCTjz95mZnxDvgSzOVbC b7+F08jl1VsoTYUDW9pqDaEK2R+GktHWPcV80IQbZ1AzBk2F6hBgkCnKncc34RIoTBtc SKDj4IINnbOayZxu8GGwgsmOn2NIMXd4gnJ3Y4tU2JJ1MvN/vdSipBVbjwvHe67J10fc nLIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:subject:cc:to:from:date:references:in-reply-to :message-id:mime-version:user-agent:dkim-signature:dkim-signature; bh=2hN+Y6whIltMm10I8URjSpg82Tc2xNvQpJgef9e0Lso=; b=TmlGFJBT+mQ9GYK6jwrFyRHqfaltsTynCbYhaQgPIrVJ/iDLlcHezIDfkN+h2PBaef zAqRT5kUjbMX4hn3gXcUEnp8AB/xuRcdk4NrNOmYcP/0dPYoYq32mfxUvRNTW1H2OpzC 4s971bWDVAREYe5ycLzBUlNDdg0BUVHSImGXIw+8jqxqoEzE5qoG2JLRy4zXLnD1Ekd8 F68iluyV1jB9nGyixCbZVidfDrdjid18nSN5OSmkFRjvlXOL6YEN769zsuHdLPw2S5zG UNBO7cY3JhjPAZgz7fGm4e63ACM42CDflBcILAiWjmdAmDZeyfusmM9HNveZD8KNCfUB b2mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@svenpeter.dev header.s=fm1 header.b=3yxm8ZMx; dkim=pass header.i=@messagingengine.com header.s=fm2 header.b="E+E/wiF5"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=svenpeter.dev Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z8si9792920edd.377.2021.05.30.04.10.02; Sun, 30 May 2021 04:10:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@svenpeter.dev header.s=fm1 header.b=3yxm8ZMx; dkim=pass header.i=@messagingengine.com header.s=fm2 header.b="E+E/wiF5"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=svenpeter.dev Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229769AbhE3LKn (ORCPT + 99 others); Sun, 30 May 2021 07:10:43 -0400 Received: from new3-smtp.messagingengine.com ([66.111.4.229]:44003 "EHLO new3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229500AbhE3LKl (ORCPT ); Sun, 30 May 2021 07:10:41 -0400 Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailnew.nyi.internal (Postfix) with ESMTP id 31C255849E1; Sun, 30 May 2021 07:09:03 -0400 (EDT) Received: from imap21 ([10.202.2.71]) by compute3.internal (MEProxy); Sun, 30 May 2021 07:09:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svenpeter.dev; h=mime-version:message-id:in-reply-to:references:date:from:to :cc:subject:content-type; s=fm1; bh=2hN+Y6whIltMm10I8URjSpg82Tc2 xNvQpJgef9e0Lso=; b=3yxm8ZMxOOpax8We+5bmJ1kcUXGO118hg7ilPzQ8Pdyp 1RUu/oUotRGBMHONPuHAl6HLJIkwfYvGj6JVCvWPg1X7244159mygY0xi9ujZWV1 /GSOdilq9hDIJRU2ScziiwR/U21hQwxUcZzlp1MWOACYPwKVRFMzFclSp35B78qz s75lF7q+Eog0U8AhEsuSpF//QMtZo0r+JFa5Dw3O6nvVlGzIiDZK6L+LrlnHi9mi ZLoAcbSlezBYH2SB6a8ETeTf2HZCiFnb0J4JLReFDsA4hUjQU8vj/CKKoZExrTzL uy3XjavLMsDa5ITwglUMrC+aOgqRXOmu2T+qR1cW/A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=2hN+Y6 whIltMm10I8URjSpg82Tc2xNvQpJgef9e0Lso=; b=E+E/wiF5bQgY4EgKydN4PM A1KAWksDctqpsGZ3nqW0O+o5OMMBaLmg2jT8VNsXYHA21giDbk1ppJzxpCSD2dw9 EJR+xx9wg0OFbBEyCJbQQcb1IrlWPJkJ50PPYYBWkBFNKET1fW97BFrJ99U5r110 gtF3FCBIMYVtNDfCD45xFULbBoWQeXlewrBNbWdaueKB1Gscm0SF3HRw6K6MAVvx 8GkEhpQ8TMR2mhcAP1D7oHM0ZaCww/2iTf2ksYsHHHiraPYxpIqUJh9b11DVvZT7 Gy4MkxiQDj+uGpE//2o1C1T5mDcKt46e/Yv1dcCxfS2+anl+kSM/LrWJvffXVaiA == X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrvdeluddgfeejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepofgfggfkjghffffhvffutgesthdtredtreertdenucfhrhhomhepfdfuvhgv nhcurfgvthgvrhdfuceoshhvvghnsehsvhgvnhhpvghtvghrrdguvghvqeenucggtffrrg htthgvrhhnpefgieegieffuefhtedtjefgteejteefleefgfefgfdvvddtgffhffduhedv feekffenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpe hsvhgvnhesshhvvghnphgvthgvrhdruggvvh X-ME-Proxy: Received: by mailuser.nyi.internal (Postfix, from userid 501) id DF48F51C0060; Sun, 30 May 2021 07:09:01 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.5.0-alpha0-468-gdb53729b73-fm-20210517.001-gdb53729b Mime-Version: 1.0 Message-Id: <9ff6ec26-4b78-4684-9c23-16d5cbfef857@www.fastmail.com> In-Reply-To: References: <20210524182745.22923-1-sven@svenpeter.dev> Date: Sun, 30 May 2021 13:08:40 +0200 From: "Sven Peter" To: "Tony Lindgren" , "Rob Herring" Cc: devicetree@vger.kernel.org, linux-clk , linux-arm-kernel , "linux-kernel@vger.kernel.org" , "Hector Martin" , "Michael Turquette" , "Stephen Boyd" , "Mark Kettenis" , "Arnd Bergmann" Subject: Re: [PATCH 0/3] Apple M1 clock gate driver Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Wed, May 26, 2021, at 09:18, Tony Lindgren wrote: > Hi, > > * Rob Herring [210525 18:09]: > > I would do a single node per mmio region with the register offset (or > > offset / 4) being the clock id. This can still support new SoCs easily > > if you have a fallback compatible. If you want/need to get all the > > clocks, just walk the DT 'clocks' properties and extract all the IDs. > > I mostly agree.. Except I'd also leave out the artificial clock ID and > just use real register offsets from the clock controller base instead. Sure, I'll do that. > > So a single clock controller node for each MMIO range, then set > #clock=cells = <1>. Then the binding follows what we have for the > interrupts-extended binding for example. > > If the clock controller optionally needs some data in the dts, > that can be added to the clock controller node. Or it can be driver > internal built-in data. If the data for dts can be described in a > generic way, even better :) Now the big question is *how* to describe this additional data in the dts. Essentially I need to specify that e.g. to enable clock 0x270 I first need to enable the (internal) clocks 0x1c0 and then 0x220. Are you aware of any generic way to describe this? I'm not even sure how a sane non-generic way would look like when I just have a single clock controller node. Best, Sven