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From:   Ming Qian <ming.qian@nxp.com>
To:     Nicolas Dufresne <nicolas@ndufresne.ca>,
        "mchehab@kernel.org" <mchehab@kernel.org>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
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        "festevam@gmail.com" <festevam@gmail.com>,
        dl-linux-imx <linux-imx@nxp.com>,
        Aisheng Dong <aisheng.dong@nxp.com>,
        "linux-media@vger.kernel.org" <linux-media@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>
Subject: RE: [EXT] Re: [PATCH 1/5] dt-bindings: media: imx8q: add imx video
 codec bindings
Thread-Topic: [EXT] Re: [PATCH 1/5] dt-bindings: media: imx8q: add imx video
 codec bindings
Thread-Index: AQHXVcfqGsnUGl1w80aC15AYWxJrYKr9qyoAgAC4eaA=
Date:   Tue, 1 Jun 2021 01:48:28 +0000
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> Le lundi 31 mai 2021 =E0 10:51 +0800, Ming Qian a =E9crit :
> > Add devicetree binding documentation for IMX8Q Video Processing Unit
> > IP
> >
> > Signed-off-by: Ming Qian <ming.qian@nxp.com>
> > Signed-off-by: Shijie Qin <shijie.qin@nxp.com>
> > Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
> > ---
> >  .../bindings/media/nxp,imx8q-vpu.yaml         | 201
> ++++++++++++++++++
> >  1 file changed, 201 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
> > b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
> > new file mode 100644
> > index 000000000000..97e428dbfdbe
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
> > @@ -0,0 +1,201 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +
> > +%YAML 1.2
> > +---
> > +$id:
> > +https://eur01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fdev=
i
> >
> +cetree.org%2Fschemas%2Fmedia%2Fnxp%2Cimx8q-vpu.yaml%23&amp;data
> =3D04%7C
> >
> +01%7Cming.qian%40nxp.com%7C8420b2323fb844ffb7ab08d924428216%7
> C686ea1d
> >
> +3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637580690330635265%7CUnk
> nown%7CTW
> >
> +FpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX
> VCI
> >
> +6Mn0%3D%7C1000&amp;sdata=3D5D8DWb4rqnARSlauGRZ838IHPH2mHJ6wG
> GKG4688gVM%
> > +3D&amp;reserved=3D0
> > +$schema:
> > +https://eur01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fdev=
i
> >
> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=3D04%7C01%7Cmin
> g.qian
> >
> +%40nxp.com%7C8420b2323fb844ffb7ab08d924428216%7C686ea1d3bc2b4
> c6fa92cd
> >
> +99c5c301635%7C0%7C0%7C637580690330635265%7CUnknown%7CTWFp
> bGZsb3d8eyJW
> >
> +IjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C
> 1000
> >
> +&amp;sdata=3DE0eIlneiBMKtz2EA%2FgFESzElq2k57nLt7u36J2n51gw%3D&amp
> ;reser
> > +ved=3D0
> > +
> > +title: NXP i.MX8Q video encode and decode accelerators
> > +
> > +maintainers:
> > +  - ming_qian <ming.qian@nxp.com>
> > +  - Shijie Qin <shijie.qin@nxp.com>
> > +
> > +description: |-
> > +  The Amphion MXC video encode and decode accelerators present on NXP
> i.MX8Q SoCs.
>=20
> Hi, thanks for this work. Do you think it would be possible to give a ver=
sion for
> the Amphion design that is in used ? This is for the posterity and/or if =
some
> non-NXP vendor needs to use this driver because it picked the same design=
.
> Though form what I understood, Allegro acquired it, and might not be
> continuing that model, it remains that is nicer if we document as much as=
 we
> can, to give maximum relevance to you rcontribution.

Hi Nicolas,
  We will add the description of the version for the Amphion IP in the V2 p=
atch, thank you for your advice

>=20
> > +
> > +allOf:
> > +  - $ref: /schemas/simple-bus.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +        - nxp,imx8qxp-vpu
> > +        - nxp,imx8qm-vpu
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  memory-region:
> > +    description:
> > +      Phandle to a node describing reserved memory used by VPU.
> > +      (see bindings/reserved-memory/reserved-memory.txt)
> > +
> > +  vpu_lpcg:
> > +    description:
> > +      This is vpu Low-Power Clock Gate (LPCG) module.
> > +
> > +  mu_m0:
> > +    description:
> > +      Each vpu core correspond a MU node, which used for
> communication between
> > +      driver and firmware. Implement via mailbox on driver.
> > +
> > +    vpu_core:
> > +      type: object
> > +      additionalProperties: false
> > +      description:
> > +        Each core correspond a decoder or encoder, need to configure
> them
> > +        separately.
> > +
> > +      properties:
> > +        compatible:
> > +          oneOf:
> > +            - const: nxp,imx8q-vpu-decoder
> > +            - const: nxp,imx8q-vpu-encoder
> > +
> > +        reg:
> > +          maxItems: 1
> > +
> > +        power-domains:
> > +          maxItems: 1
> > +
> > +        mbox-names:
> > +            - const: tx0
> > +            - const: tx1
> > +            - const: rx
> > +
> > +        mboxes:
> > +          maxItems: 3
> > +          description:
> > +            List of phandle of 2 MU channels for tx, 1 MU channel for =
rx.
> > +
> > +        boot-region:
> > +          description:
> > +            Phandle to a node describing reserved memory used by
> firmware
> > +            loading.
> > +
> > +        rpc-region:
> > +          description:
> > +            Phandle to a node describing reserved memory used by RPC
> shared
> > +            memory between firmware and driver.
> > +
> > +        print-offset:
> > +          description:
> > +            The memory offset from RPC address, used by reserve
> firmware log.
> > +
> > +        id:
> > +          description: Index of vpu core.
> > +
> > +      required:
> > +      - compatible
> > +      - reg
> > +      - power-domains
> > +      - mbox-names
> > +      - mboxes
> > +      - boot-region
> > +      - rpc-region
> > +      - print-offset
> > +      - id
> > +
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - power-domains
> > +  - memory-region
> > +  - vpu_lpcg
> > +  - mu_m0
> > +  - vpu_core
> > +
> > +examples:
> > +  # Device node example for i.MX8QM platform:
> > +  - |
> > +    #include <dt-bindings/firmware/imx/rsrc.h>
> > +
> > +    vpu: vpu-bus@2c000000 {
> > +      compatible =3D "nxp,imx8qm-vpu", "simple-bus";
> > +      ranges =3D <0x2c000000 0x2c000000 0x2000000>;
> > +      reg =3D <0x2c000000 0x1000000>;
> > +      #address-cells =3D <1>;
> > +      #size-cells =3D <1>;
> > +      power-domains =3D <&pd IMX_SC_R_VPU>;
> > +      memory-region =3D <&vpu_reserved>;
> > +
> > +      vpu_lpcg: clock-controller@2c000000 {
> > +        compatible =3D "fsl,imx8qxp-lpcg-vpu";
> > +        reg =3D <0x2c000000 0x2000000>;
> > +        #clock-cells =3D <1>;
> > +        status =3D "disabled";
> > +      };
> > +
> > +      mu_m0: mailbox@2d000000 {
> > +        compatible =3D "fsl,imx6sx-mu";
> > +        reg =3D <0x2d000000 0x20000>;
> > +        interrupts =3D <0 472 4>;
> > +        #mbox-cells =3D <2>;
> > +        power-domains =3D <&pd IMX_SC_R_VPU_MU_0>;
> > +      };
> > +
> > +      mu1_m0: mailbox@2d020000 {
> > +        compatible =3D "fsl,imx6sx-mu";
> > +        reg =3D <0x2d020000 0x20000>;
> > +        interrupts =3D <0 473 4>;
> > +        #mbox-cells =3D <2>;
> > +        power-domains =3D <&pd IMX_SC_R_VPU_MU_1>;
> > +      };
> > +
> > +      mu2_m0: mailbox@2d040000 {
> > +        compatible =3D "fsl,imx6sx-mu";
> > +        reg =3D <0x2d040000 0x20000>;
> > +        interrupts =3D <0 474 4>;
> > +        #mbox-cells =3D <2>;
> > +        power-domains =3D <&pd IMX_SC_R_VPU_MU_2>;
> > +      };
> > +
> > +      vpu_core0: vpu_decoder@2d080000 {
> > +        compatible =3D "nxp,imx8q-vpu-decoder";
> > +        reg =3D <0x2d080000 0x10000>;
> > +        power-domains =3D <&pd IMX_SC_R_VPU_DEC_0>;
> > +        mbox-names =3D "tx0", "tx1", "rx";
> > +        mboxes =3D <&mu_m0 0 0
> > +                  &mu_m0 0 1
> > +                  &mu_m0 1 0>;
> > +        boot-region =3D <&decoder_boot>;
> > +        rpc-region =3D <&decoder_rpc>;
> > +        print-offset =3D <0x180000>;
> > +        id =3D <0>;
> > +      };
> > +
> > +      vpu_core1: vpu_encoder@2d090000 {
> > +        compatible =3D "nxp,imx8q-vpu-encoder";
> > +        reg =3D <0x2d090000 0x10000>;
> > +        power-domains =3D <&pd IMX_SC_R_VPU_ENC_0>;
> > +        mbox-names =3D "tx0", "tx1", "rx";
> > +        mboxes =3D <&mu1_m0 0 0
> > +                  &mu1_m0 0 1
> > +                  &mu1_m0 1 0>;
> > +        boot-region =3D <&encoder1_boot>;
> > +        rpc-region =3D <&encoder1_rpc>;
> > +        print-offset =3D <0x80000>;
> > +        id =3D <1>;
> > +      };
> > +
> > +      vpu_core2: vpu_encoder@2d0a0000 {
> > +        reg =3D <0x2d0a0000 0x10000>;
> > +        compatible =3D "nxp,imx8q-vpu-encoder";
> > +        power-domains =3D <&pd IMX_SC_R_VPU_ENC_1>;
> > +        mbox-names =3D "tx0", "tx1", "rx";
> > +        mboxes =3D <&mu2_m0 0 0
> > +                  &mu2_m0 0 1
> > +                  &mu2_m0 1 0>;
> > +        boot-region =3D <&encoder2_boot>;
> > +        rpc-region =3D <&encoder2_rpc>;
> > +        id =3D <2>;
> > +      };
> > +    };
> > +
> > +...
>=20