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From:   Ard Biesheuvel <ardb@kernel.org>
Date:   Tue, 1 Jun 2021 07:49:05 +0200
Message-ID: <CAMj1kXHkZhgp3y_1dvKjfiEbwWDooCY0X+0HZutn5ZrsRGk15w@mail.gmail.com>
Subject: Re: [PATCH v2 1/4] PCI: of: Override 64-bit flag for non-prefetchable
 memory below 4GB
To:     Punit Agrawal <punitagrawal@gmail.com>
Cc:     "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        PCI <linux-pci@vger.kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Alexandru Elisei <alexandru.elisei@arm.com>, wqu@suse.com,
        Robin Murphy <robin.murphy@arm.com>,
        Peter Geis <pgwipeout@gmail.com>, briannorris@chromium.org,
        shawn.lin@rock-chips.com, Bjorn Helgaas <helgaas@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>
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Hi Punit,

On Tue, 1 Jun 2021 at 00:11, Punit Agrawal <punitagrawal@gmail.com> wrote:
>
> Some host bridges advertise non-prefetable memory windows that are

typo ^

> entirely located below 4GB but are marked as 64-bit address memory.
>
> Since commit 9d57e61bf723 ("of/pci: Add IORESOURCE_MEM_64 to resource
> flags for 64-bit memory addresses"), the OF PCI range parser takes a
> stricter view and treats 64-bit address ranges as advertised while
> before such ranges were treated as 32-bit.
>
> A PCI host bridge that is modelled as PCI-to-PCI bridge cannot forward

It is the root port which is modeled as a P2P bridge. The root port(s)
together with the host bridge is what makes up the root complex.


> 64-bit non-prefetchable memory ranges. As a result, the change in
> behaviour due to the commit causes allocation failure for devices that
> require non-prefetchable bus addresses.
>

AIUI, the problem is not that the device requires a non-prefetchable
bus address, but that it fails to allocate a 32-bit BAR from a 64-bit
non-prefetchable window.

> In order to not break platforms, override the 64-bit flag for
> non-prefetchable memory ranges that lie entirely below 4GB.
>
> Suggested-by: Ard Biesheuvel <ardb@kernel.org>
> Link: https://lore.kernel.org/r/7a1e2ebc-f7d8-8431-d844-41a9c36a8911@arm.com
> Signed-off-by: Punit Agrawal <punitagrawal@gmail.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Rob Herring <robh+dt@kernel.org>
>
> Signed-off-by: Punit Agrawal <punitagrawal@gmail.com>
> ---
>  drivers/pci/of.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> index da5b414d585a..e2e64c5c55cb 100644
> --- a/drivers/pci/of.c
> +++ b/drivers/pci/of.c
> @@ -346,6 +346,14 @@ static int devm_of_pci_get_host_bridge_resources(struct device *dev,
>                                 dev_warn(dev, "More than one I/O resource converted for %pOF. CPU base address for old range lost!\n",
>                                          dev_node);
>                         *io_base = range.cpu_addr;
> +               } else if (resource_type(res) == IORESOURCE_MEM) {
> +                       if (!(res->flags & IORESOURCE_PREFETCH)) {
> +                               if (res->flags & IORESOURCE_MEM_64)
> +                                       if (!upper_32_bits(range.pci_addr + range.size - 1)) {
> +                                               dev_warn(dev, "Clearing 64-bit flag for non-prefetchable memory below 4GB\n");
> +                                               res->flags &= ~IORESOURCE_MEM_64;
> +                                       }
> +                       }
>                 }
>
>                 pci_add_resource_offset(resources, res, res->start - range.pci_addr);
> --
> 2.30.2
>