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Tue, 1 Jun 2021 09:56:44 +0000 From: "Peng Fan (OSS)" To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, o.rempel@pengutronix.de Cc: shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, linux-remoteproc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan Subject: [PATCH] remoteproc: imx_rproc: correct firmware reload Date: Tue, 1 Jun 2021 18:29:39 +0800 Message-Id: <20210601102939.16139-1-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR0302CA0005.apcprd03.prod.outlook.com (2603:1096:3:2::15) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR0302CA0005.apcprd03.prod.outlook.com (2603:1096:3:2::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.9 via Frontend Transport; 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Besides ENABLE_M4, we still need set SW_M4C_RST, because this bit will be automatically set with SW_M4C_NON_SCLR_RST set. Signed-off-by: Peng Fan --- V1: Although this is an fix, but it is not critical, patch is based on https://patchwork.kernel.org/project/linux-remoteproc/cover/1620274123-1461-1-git-send-email-peng.fan@oss.nxp.com/ drivers/remoteproc/imx_rproc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c index cd2ca96a30e5..ce2ce42bee91 100644 --- a/drivers/remoteproc/imx_rproc.c +++ b/drivers/remoteproc/imx_rproc.c @@ -33,7 +33,8 @@ #define IMX7D_M4_START (IMX7D_ENABLE_M4 | IMX7D_SW_M4P_RST \ | IMX7D_SW_M4C_RST) -#define IMX7D_M4_STOP (IMX7D_ENABLE_M4 | IMX7D_SW_M4C_NON_SCLR_RST) +#define IMX7D_M4_STOP (IMX7D_ENABLE_M4 | IMX7D_SW_M4C_RST | \ + IMX7D_SW_M4C_NON_SCLR_RST) /* Address: 0x020D8000 */ #define IMX6SX_SRC_SCR 0x00 @@ -44,7 +45,8 @@ #define IMX6SX_M4_START (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \ | IMX6SX_SW_M4C_RST) -#define IMX6SX_M4_STOP (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4C_NON_SCLR_RST) +#define IMX6SX_M4_STOP (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4C_RST | \ + IMX6SX_SW_M4C_NON_SCLR_RST) #define IMX6SX_M4_RST_MASK (IMX6SX_ENABLE_M4 | IMX6SX_SW_M4P_RST \ | IMX6SX_SW_M4C_NON_SCLR_RST \ | IMX6SX_SW_M4C_RST) @@ -691,7 +693,7 @@ static int imx_rproc_detect_mode(struct imx_rproc *priv) return ret; } - if (!(val & dcfg->src_stop)) + if ((val & dcfg->src_mask) != dcfg->src_stop) priv->rproc->state = RPROC_DETACHED; return 0; -- 2.30.0