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From:   Parav Pandit <parav@nvidia.com>
To:     Jason Gunthorpe <jgg@nvidia.com>
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Subject: RE: [RFC] /dev/ioasid uAPI proposal
Thread-Topic: [RFC] /dev/ioasid uAPI proposal
Thread-Index: AddSzQ970oLnVHLeQca/ysPD8zMJZwDdOxjAAAGkOoAAJToGkA==
Date:   Tue, 1 Jun 2021 12:04:00 +0000
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> From: Jason Gunthorpe <jgg@nvidia.com>
> Sent: Monday, May 31, 2021 11:43 PM
>=20
> On Mon, May 31, 2021 at 05:37:35PM +0000, Parav Pandit wrote:
>=20
> > In that case, can it be a new system call? Why does it have to be under
> /dev/ioasid?
> > For example few years back such system call mpin() thought was proposed
> in [1].
>=20
> Reference counting of the overall pins are required
>=20
> So when a pinned pages is incorporated into an IOASID page table in a lat=
er
> IOCTL it means it cannot be unpinned while the IOASID page table is using=
 it.
Ok. but cant it use the same refcount of that mmu uses?

>=20
> This is some trick to organize the pinning into groups and then refcount =
each
> group, thus avoiding needing per-page refcounts.
Pinned page refcount is already maintained by the mmu without ioasid, isn't=
 it?

>=20
> The data structure would be an interval tree of pins in general
>=20
> The ioasid itself would have an interval tree of its own mappings, each e=
ntry
> in this tree would reference count against an element in the above tree
>=20
> Then the ioasid's interval tree would be mapped into a page table tree in=
 HW
> format.
Does it mean in simple use case [1], second level page table copy is mainta=
ined in the IOMMU side via map interface?
I hope not. It should use the same as what mmu uses, right?

[1] one SIOV/ADI device assigned with one PASID and mapped in guest VM

>=20
> The redundant storages are needed to keep track of the refencing and the
> CPU page table values for later unpinning.
>=20
> Jason