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[23.128.96.18]) by mx.google.com with ESMTP id v3si3904988jao.58.2021.06.01.07.20.36; Tue, 01 Jun 2021 07:20:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@ffwll.ch header.s=google header.b=dRqQy1u9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234210AbhFAOUj (ORCPT + 99 others); Tue, 1 Jun 2021 10:20:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233797AbhFAOUi (ORCPT ); Tue, 1 Jun 2021 10:20:38 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7027CC061574 for ; Tue, 1 Jun 2021 07:18:56 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id o2-20020a05600c4fc2b029019a0a8f959dso2035306wmq.1 for ; Tue, 01 Jun 2021 07:18:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=date:from:to:cc:subject:message-id:mail-followup-to:references :mime-version:content-disposition:in-reply-to; bh=788TRfnbUrWf/WZzHLMqqD0WkTRUfs23Xy3cmXUca3E=; b=dRqQy1u9vF65GRNZlxfjsnv8Y5iRPCoy2GN00LMqPsx2FjMW+fcu4QwrALoz3oL/8V C9c0yVqwelZITiACOVgMWNy/JUnI5d/NeK8yogc5jJVRKY1T3rAISZ27u68Zd0fx2xmL /ALfLx3ncWHDRIhFOs4hEVKf2QVpk2QqDTiNA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id :mail-followup-to:references:mime-version:content-disposition :in-reply-to; bh=788TRfnbUrWf/WZzHLMqqD0WkTRUfs23Xy3cmXUca3E=; b=CKUSsp/VHnegY4j15gjbZZsn77+LqoxEVxfXdFR1zKaTj8FLTZ4wAKlLYGDddSeciy NVIgVjhbMimClLuCmX3AF1S3pcHbyNAexaY74Od6JLMlIA8Iw5zvBIrp9DUdC69NSx/9 WnUOS2k94kwQQLuRE9lIlmRikITGqP1/zIj323vZYgwj7ZPt5mEhvN+Ew/buZaBNe9Kg At/nokcIVM9avbgZazzV7PCU3v6rQm79vWsl7fiVd0V0N+11gVCaLJcYdCPvVZOpPHJK xqsU+qpBNCVVQViM2uIyySfKuhLml5Y6xaGhA2TlyDBKqPr8xPrikXY5vYgh8AeURIjr OBLw== X-Gm-Message-State: AOAM530Gw21YIJ5TbZp56ARWxz9FPCa4247oIKwDj4PQrTnBHvOllzzE d9PvCVseEEpdAgL554c8yJt38Q== X-Received: by 2002:a05:600c:4ec9:: with SMTP id g9mr25760736wmq.173.1622557135056; Tue, 01 Jun 2021 07:18:55 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:57f4:0:efd0:b9e5:5ae6:c2fa]) by smtp.gmail.com with ESMTPSA id t4sm1874151wru.53.2021.06.01.07.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jun 2021 07:18:54 -0700 (PDT) Date: Tue, 1 Jun 2021 16:18:52 +0200 From: Daniel Vetter To: Rob Clark Cc: dri-devel , freedreno , linux-arm-msm , Rob Clark , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , open list , Matthew Brost , Daniel Vetter Subject: Re: [RFC 2/3] drm/atomic: Call dma_fence_boost() when we've missed a vblank Message-ID: Mail-Followup-To: Rob Clark , dri-devel , freedreno , linux-arm-msm , Rob Clark , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , open list , Matthew Brost References: <20210519183855.1523927-1-robdclark@gmail.com> <20210519183855.1523927-3-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Operating-System: Linux phenom 5.10.32scarlett+ Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, May 30, 2021 at 07:33:57AM -0700, Rob Clark wrote: > On Thu, May 20, 2021 at 9:29 AM Daniel Vetter wrote: > > > > On Wed, May 19, 2021 at 11:38:53AM -0700, Rob Clark wrote: > > > From: Rob Clark > > > > > > Signed-off-by: Rob Clark > > > --- > > > drivers/gpu/drm/drm_atomic_helper.c | 11 +++++++++++ > > > 1 file changed, 11 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c > > > index 560aaecba31b..fe10fc2e7f86 100644 > > > --- a/drivers/gpu/drm/drm_atomic_helper.c > > > +++ b/drivers/gpu/drm/drm_atomic_helper.c > > > @@ -1435,11 +1435,15 @@ int drm_atomic_helper_wait_for_fences(struct drm_device *dev, > > > int i, ret; > > > > > > for_each_new_plane_in_state(state, plane, new_plane_state, i) { > > > + u64 vblank_count; > > > + > > > if (!new_plane_state->fence) > > > continue; > > > > > > WARN_ON(!new_plane_state->fb); > > > > > > + vblank_count = drm_crtc_vblank_count(new_plane_state->crtc); > > > + > > > /* > > > * If waiting for fences pre-swap (ie: nonblock), userspace can > > > * still interrupt the operation. Instead of blocking until the > > > @@ -1449,6 +1453,13 @@ int drm_atomic_helper_wait_for_fences(struct drm_device *dev, > > > if (ret) > > > return ret; > > > > > > + /* > > > + * Check if we've missed a vblank while waiting, and if we have > > > + * signal the fence that it's signaler should be boosted > > > + */ > > > + if (vblank_count != drm_crtc_vblank_count(new_plane_state->crtc)) > > > + dma_fence_boost(new_plane_state->fence); > > > > I think we should do a lot better here: > > - maybe only bother doing this for single-crtc updates, and only if > > modeset isn't set. No one else cares about latency. > > > > - We should boost _right_ when we've missed the frame, so I think we > > should have a _timeout wait here that guesstimates when the vblank is > > over (might need to throw in a vblank wait if we missed) and then boost > > immediately. Not wait a bunch of frames (worst case) until we finally > > decide to boost. > > I was thinking about this a bit more.. How about rather than calling > some fence->op->boost() type thing when we are about to miss a vblank > (IMO that is also already too late), we do something more like > fence->ops->set_deadline() before we even wait? Hm yeah that sounds like a clean idea. Even more, why not add the deadline/waiter information to the callback we're adding? That way drivers can inspect it whenever they feel like and don't have to duplicate the tracking. And it's probably easier to tune/adjust to the myriads of use-cases (flip target miss, userspace wait, wakeup boost maybe too ...). I like this direction a lot more than what we discussed with post-miss hints thus far. > It's probably a bit impossible for a gpu driver to really predict how > long some rendering will take, but other cases like video decoder are > somewhat more predictable.. the fence provider could predict given the > remaining time until the deadline what clk rates are required to get > you there. Well if we do have a deadline the driver can note that in its scheduler and arm a driver to kick the clocks. Or maybe use past history to do this upfront. -Daniel > > BR, > -R > > > > > > Otherwise I really like this, I think it's about the only real reason i915 > > isn't using atomic helpers. > > > > Also adding Matt B for this topic. > > -Daniel > > > > > + > > > dma_fence_put(new_plane_state->fence); > > > new_plane_state->fence = NULL; > > > } > > > -- > > > 2.30.2 > > > > > > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > http://blog.ffwll.ch -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch