Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp63596pxj; Tue, 1 Jun 2021 15:14:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyK/xL8uymfU13n5yNC/5vn6nvBCOpZHIOIF7faa+76Z9XYGLOkEYn4+0WW6Pwdwg/eQO9h X-Received: by 2002:a92:1a0b:: with SMTP id a11mr17537855ila.273.1622585644396; Tue, 01 Jun 2021 15:14:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622585644; cv=none; d=google.com; s=arc-20160816; b=b5VutjCXfInA6I4qT9UEiMsLJu4YZENoXnpFvZ+KcnZ7wL0Jyl6Sgge0lD4AhAC/TR Jn9OLvNbKdY3nK3YIz2e6N0lbccGhKhhZBHQeAB81whuyt5wR2ZWHiUTVy37SUso2QIX xRVGo/Mmfs0jAfhWZ/vkHmx69DQ+Txihn+4Pubmuz1whP3IwnCScw68P/uxs37nNwmtp NXaBEw/dxUzlsXD6qz8NirukHO5e30EKTBmxXXVL3olYUUK9hr6Jrx/Vos7HLbiPcJKu TE0YMaC/5dLG2kbtl2CJ1YO//1f+44SVFu+lESW0lAl7GvFdzKPDe6MOcGXJHn834Lw8 02GA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=y8LwDyWYmv5YNXiWo6XrFDujLoYra5BDGywMvk5NFl4=; b=Isvw9eKEsf+jhBSUBcMeWiddJuFuVgwW3n/hFziACGl/z8Kbe9DIZzpuNnBDlPs2Y5 tCQiQp9vedPI45fJsVdN1j5hBWdERuUkpxEAbpG4MXnwMYHdnbozO5PyK7WvUnxWYsAX +50R5iLPcZH2YFbF6ne4OGtGaDaa1OMk9Yl8qaPUpDTrLPIQeIXVtGaF+cL7D7O9Ikvh t3lhR6A+PvtD/+YSDqhMoOa2Mtllt4mutbfWsvJpC+JIz9CCkbV2y338y63MWuOYcqlJ p08hgClPgwJ5p3BWTa+Yce/gOL6yskAUjUJaCDQalJgtysayitY08PoNiMFTHcK5oTKE AiEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b=jlhGbIHA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r21si5935766jai.29.2021.06.01.15.13.39; Tue, 01 Jun 2021 15:14:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b=jlhGbIHA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234942AbhFAWNw (ORCPT + 99 others); Tue, 1 Jun 2021 18:13:52 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:39694 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234740AbhFAWNv (ORCPT ); Tue, 1 Jun 2021 18:13:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=y8LwDyWYmv5YNXiWo6XrFDujLoYra5BDGywMvk5NFl4=; b=jlhGbIHApiEzg8PFSvdCwdNYui KPnwoVWetNNnsKN60MmkBoMmIIb87Wbd+txqaGZbkddmlO6FSTdIkZUY7ha14fhKxWuBm056Lphz3 EEq5Wg42Q4Glb60n0KCgtfJBUyFVsJ0w42esrPhiOxu7RuUo0bVQ+9ybBIPvwXWIkB+g=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1loCc9-007M0b-84; Wed, 02 Jun 2021 00:11:57 +0200 Date: Wed, 2 Jun 2021 00:11:57 +0200 From: Andrew Lunn To: Wong Vee Khee Cc: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Jakub Kicinski , Maxime Coquelin , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next 1/1] net: stmmac: enable platform specific safety features Message-ID: References: <20210601135235.1058841-1-vee.khee.wong@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210601135235.1058841-1-vee.khee.wong@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 01, 2021 at 09:52:35PM +0800, Wong Vee Khee wrote: > On Intel platforms, not all safety features are enabled on the hardware. Is it possible to read a register is determine what safety features have been synthesised? Andrew