Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp207370pxj; Tue, 1 Jun 2021 19:29:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzh8h/eT/uCNF/tzY0d2F7/q1Ze9ZllRFC2Z1mvgpv+YKbAed5iysHEy/Auy4fSv7cknBw8 X-Received: by 2002:a05:6e02:1ba2:: with SMTP id n2mr25754986ili.60.1622600990713; Tue, 01 Jun 2021 19:29:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622600990; cv=none; d=google.com; s=arc-20160816; b=GFLlf7hY47SS1xZOwYkDwcnZQsz2CrHh6ZT5BbtT1LVhcg29JZy/mT5zKiV3b1a6cM jQ6wIt4xE2xuexz7Y0O7Gz2EaCVcPtOxqGeO7wRRjvAgrNQAJkybWmLZLOZEdd7VFEpc w8aVtLDK21ZKZ5YbT6EHGrXl8tJu1fHM69Q4TBGGS9eY1joyHADCuZwL5xqVKqvHRmCj dxjO5EUnreDPKzFy0zOGboV+aR4IgBcz2KPuuAtCv8w0hRb3hPOCSsZyyUx5uoEQqrrb opF+/2lfNqebcF4GS9EysBvu9j1g/RHbzujP/4hX3IkOzWU3pDunKSmJ7FrB6rcb3bPc gu4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=4JoMGfga1VbTByDb+krUTuutqYAcuOdoQ70Y27jTzf8=; b=FTs7z5ZFewCCYygbt+ZEfvYdSorbr0IZtJcq7b5/DepizKfNBfNdAdUXDdgHMTIsTN rdNxINx8rLWc5lr83CfMiT+oyrZp7wjR3sXUf5FHfCXzRJgnt3leu0GGiJ+vfLk4XqOz 85jg6E2jyti9SsmP3/GvQgMkjEtTMriTtnJVNVkVzhof3zFnJ9C7Dbx+NXL2JQEOK7Q0 GLXqD9MLIgpScvOCJz59D/v+bynISaWuLdZBpQdRKOliLv+NodtHYpVGBU8LXNscDwDH Dh0CwMgwfO9BN+q9vv7HDQvaEnAE100k9hqDM2rdzds4oN7Y+dv6HcUFB+c/yrE5sQ3Q eTYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b="fJXgFc/G"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q10si21342036ilu.60.2021.06.01.19.29.38; Tue, 01 Jun 2021 19:29:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@lunn.ch header.s=20171124 header.b="fJXgFc/G"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230189AbhFBCaM (ORCPT + 99 others); Tue, 1 Jun 2021 22:30:12 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:40078 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229828AbhFBCaM (ORCPT ); Tue, 1 Jun 2021 22:30:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=4JoMGfga1VbTByDb+krUTuutqYAcuOdoQ70Y27jTzf8=; b=fJXgFc/GRD6OG68GN6GC7fmcNJ sCxWFlYEPPu4yPMgLkS+5YrzUpNY5fCDZ0fhqbHEIo9tjUD3owCdEJNgisENn7quOI6GK7UPcesrt 1I8Qv271k43/RVjJiIT/byYplg7l0n5DINSoQjQynWPfsSi4PXfnM+ZMOGjUgGwdSuSs=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1loGcD-007NlP-ME; Wed, 02 Jun 2021 04:28:17 +0200 Date: Wed, 2 Jun 2021 04:28:17 +0200 From: Andrew Lunn To: Wong Vee Khee Cc: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Jakub Kicinski , Maxime Coquelin , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next 1/1] net: stmmac: enable platform specific safety features Message-ID: References: <20210601135235.1058841-1-vee.khee.wong@linux.intel.com> <20210601225332.GA28151@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210601225332.GA28151@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 02, 2021 at 06:53:32AM +0800, Wong Vee Khee wrote: > On Wed, Jun 02, 2021 at 12:11:57AM +0200, Andrew Lunn wrote: > > On Tue, Jun 01, 2021 at 09:52:35PM +0800, Wong Vee Khee wrote: > > > On Intel platforms, not all safety features are enabled on the hardware. > > > > Is it possible to read a register is determine what safety features > > have been synthesised? > > > > No. The value of these registers after reset are 0x0. We need to set it > manually. That is not what i asked. Sometimes with IP you synthesise from VHDL or Verilog, there are registers which describe which features you have actually enabled/disabled in the synthesis. Maybe the stmmac has such a register describing which safety features are actually available in your specific version of the IP? You could go ask your ASIC engineers. Or maybe Synopsys can say that there are no such registers. Andrew