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[23.128.96.18]) by mx.google.com with ESMTP id g5si10125963ilr.52.2021.06.02.01.05.59; Wed, 02 Jun 2021 01:06:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229881AbhFBFFj (ORCPT + 99 others); Wed, 2 Jun 2021 01:05:39 -0400 Received: from muru.com ([72.249.23.125]:35156 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229863AbhFBFFi (ORCPT ); Wed, 2 Jun 2021 01:05:38 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 3864E80E0; Wed, 2 Jun 2021 05:04:01 +0000 (UTC) Date: Wed, 2 Jun 2021 08:03:51 +0300 From: Tony Lindgren To: Linus Walleij Cc: Dario Binacchi , Vladimir Zapolskiy , linux-kernel , Drew Fustini , Andy Shevchenko , "open list:GPIO SUBSYSTEM" Subject: Re: [PATCH v3 2/3] pinctrl: core: configure pinmux from pins debug file Message-ID: References: <20210520202730.4444-1-dariobin@libero.it> <20210520202730.4444-3-dariobin@libero.it> <87ea9971-9e15-c595-95cc-14c68b0b68d8@mleia.com> <1972814783.387983.1621877304255@mail1.libero.it> <414c9176-7922-929f-e82e-f80f07e91b2c@mleia.com> <106030092.519428.1622143415836@mail1.libero.it> <2062056721.520514.1622147634190@mail1.libero.it> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Linus Walleij [210528 09:08]: > On Thu, May 27, 2021 at 10:33 PM Dario Binacchi wrote: > > > Il 27/05/2021 21:57 Vladimir Zapolskiy ha scritto: > > > > Unfortunately you continue to cling to the broken interface, while I see no > > > comments from you about asked to consider pin groups and pin group functions. > > > > Could you kindly explain to me, with some practical examples, what kind of interface > > would you implement ? > > I am not fully understanding this discussion. > > I get the feeling that this is caused by the early architectural decisions with > pinctrl-single to put all configuration of pin groups and functions per pin into > the device tree. > > Tony specifically wanted this because what he gets from TI are some raw > ASIC data dumps from the designers, that he could make a script to process > into device tree rather than into .h files, and get this out of the kernel. > (As I remember it, Tony correct me if I'm wrong.) Yeah the idea was to avoid stuffing even more SoC specific data into the kernel and rather use devicetree data only for the booted SoC. > This makes it hard to align some concepts of the pin control subsystem such > as functions and groups because pinctrl-single assume a 1-to-1 mapping > between one pin and one group, which in turn has a 1-to-many mapping > to functions. > > Is the patch trying to debugfs around this somehow? > > If this hack is only needed for pinctrl-single.c then it should be placed in > that driver, so Tony can review it and maintain it as applicable in that > driver's context only, not in the pinctrl core as it appears the general > applicability for other drivers is not there. > > Would this really be useful for other drivers than pinctrl-single.c? I'd rather go with a generic interface. I think it should work if we only allow enabling and disabling of unclaimed pingroups from sysfs. And then we can also allow creating new pingroups for unclaimed pins if needed. Regards, Tony