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Date:   Wed, 2 Jun 2021 13:12:14 +0530
From:   Pratyush Yadav <p.yadav@ti.com>
To:     Michael Walle <michael@walle.cc>
CC:     Tudor Ambarus <tudor.ambarus@microchip.com>,
        Miquel Raynal <miquel.raynal@bootlin.com>,
        Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        Mark Brown <broonie@kernel.org>,
        <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
        <linux-spi@vger.kernel.org>
Subject: Re: [PATCH v2 2/6] mtd: spi-nor: spansion: write 2 bytes when
 disabling Octal DTR mode
Message-ID: <20210602074212.o4dmwry747wortsq@ti.com>
References: <20210531181757.19458-1-p.yadav@ti.com>
 <20210531181757.19458-3-p.yadav@ti.com>
 <f875025538713a005b1c18f8eb5c24c0@walle.cc>
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On 01/06/21 02:47PM, Michael Walle wrote:
> Am 2021-05-31 20:17, schrieb Pratyush Yadav:
> > The Octal DTR configuration is stored in the CFR5V register. This
> > register is 1 byte wide. But 1 byte long transactions are not allowed in
> > 8D-8D-8D mode. Since the next byte address does not contain any
> > register, it is safe to write any value to it. Write a 0 to it.
> > 
> > Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> > ---
> 
> Can't say much, because there is no public datasheet, is there?

https://www.cypress.com/file/513996/download

> 
> But looks sane. Same for patch 3/6.

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.