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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id 31sm7003760wrc.96.2021.06.02.03.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 03:43:42 -0700 (PDT) Date: Wed, 2 Jun 2021 10:43:40 +0000 From: Quentin Perret To: Yanan Wang Cc: Marc Zyngier , Will Deacon , Alexandru Elisei , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Catalin Marinas , James Morse , Julien Thierry , Suzuki K Poulose , Gavin Shan , wanghaibin.wang@huawei.com, zhukeqian1@huawei.com, yuzenghui@huawei.com Subject: Re: [PATCH v5 1/6] KVM: arm64: Introduce KVM_PGTABLE_S2_GUEST stage-2 flag Message-ID: References: <20210415115032.35760-1-wangyanan55@huawei.com> <20210415115032.35760-2-wangyanan55@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210415115032.35760-2-wangyanan55@huawei.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Yanan, On Thursday 15 Apr 2021 at 19:50:27 (+0800), Yanan Wang wrote: > diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h > index c3674c47d48c..a43cbe697b37 100644 > --- a/arch/arm64/include/asm/kvm_pgtable.h > +++ b/arch/arm64/include/asm/kvm_pgtable.h > @@ -61,10 +61,12 @@ struct kvm_pgtable_mm_ops { > * @KVM_PGTABLE_S2_NOFWB: Don't enforce Normal-WB even if the CPUs have > * ARM64_HAS_STAGE2_FWB. > * @KVM_PGTABLE_S2_IDMAP: Only use identity mappings. > + * @KVM_PGTABLE_S2_GUEST: Whether the page-tables are guest stage-2. > */ > enum kvm_pgtable_stage2_flags { > KVM_PGTABLE_S2_NOFWB = BIT(0), > KVM_PGTABLE_S2_IDMAP = BIT(1), > + KVM_PGTABLE_S2_GUEST = BIT(2), Assuming that we need this flag (maybe not given Marc's suggestion on another patch), I'd recommend re-naming it to explain _what_ it does, rather than _who_ is using it. That's the principle we followed for e.g. KVM_PGTABLE_S2_IDMAP, so we should be consistent here as well. Thanks, Quentin