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Wed, 2 Jun 2021 14:51:17 +0000 Received: from [172.27.1.6] (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 14:51:08 +0000 Subject: Re: [PATCH 3/3] nvme-pci: align CMB size according to P2PMEM alignment To: Keith Busch CC: , , , , , , , , , References: <20210602111055.10480-1-mgurtovoy@nvidia.com> <20210602111055.10480-4-mgurtovoy@nvidia.com> <20210602143940.GA5751@dhcp-10-100-145-180.wdc.com> From: Max Gurtovoy Message-ID: <9ff88c55-2e9c-3cec-81a5-b47b344815a4@nvidia.com> Date: Wed, 2 Jun 2021 17:51:05 +0300 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 MIME-Version: 1.0 In-Reply-To: <20210602143940.GA5751@dhcp-10-100-145-180.wdc.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d6ddeca1-9dce-4b3c-d51b-08d925d5e085 X-MS-TrafficTypeDiagnostic: BYAPR12MB3016: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:51:17.3155 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6ddeca1-9dce-4b3c-d51b-08d925d5e085 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3016 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/2/2021 5:39 PM, Keith Busch wrote: > On Wed, Jun 02, 2021 at 02:10:55PM +0300, Max Gurtovoy wrote: >> P2PMEM is using mhp framework to connect to the memory subsystem. In >> case the CMB size is not compatible to mhp alignment, the CMB mapping >> will fail. Use pci_p2pdma_align_size to align CMB size in order to >> successfully map non-aligned original CMB. >> >> Signed-off-by: Max Gurtovoy >> --- >> drivers/nvme/host/pci.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c >> index a29b170701fc..1197263b4cd0 100644 >> --- a/drivers/nvme/host/pci.c >> +++ b/drivers/nvme/host/pci.c >> @@ -1817,6 +1817,7 @@ static void nvme_map_cmb(struct nvme_dev *dev) >> u64 size, offset; >> resource_size_t bar_size; >> struct pci_dev *pdev = to_pci_dev(dev->dev); >> + unsigned long nr_pages, min_align; > These new variables don't appear to be used anywhere. oh, I have some leftovers.. Sorry. > >> int bar; >> >> if (dev->cmb_size) >> @@ -1856,6 +1857,12 @@ static void nvme_map_cmb(struct nvme_dev *dev) >> if (size > bar_size - offset) >> size = bar_size - offset; >> >> + size = pci_p2pdma_align_size(size); >> + if (!size) { >> + dev_warn(dev->ctrl.device, "CMB size is 0 after alignment\n"); >> + return; >> + } >> + >> if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { >> dev_warn(dev->ctrl.device, >> "failed to register the CMB\n"); >> --