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Date:   Thu, 3 Jun 2021 16:23:38 +0200
From:   Grzegorz Szymaszek <gszymaszek@short.pl>
To:     Alexandre Torgue <alexandre.torgue@foss.st.com>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc:     Grzegorz Szymaszek <gszymaszek@short.pl>,
        Ahmad Fatoum <a.fatoum@pengutronix.de>,
        Marcin Sloniewski <marcin.sloniewski@gmail.com>,
        Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-stm32@st-md-mailman.stormreply.com
Subject: [PATCH] ARM: dts: stm32: set stm32mp157c-odyssey DCMI pins
Message-ID: <YLjl6lE+uZ5ZCdiS@nx64de-df6d00>
Mail-Followup-To: Grzegorz Szymaszek <gszymaszek@short.pl>,
        Alexandre Torgue <alexandre.torgue@foss.st.com>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        Ahmad Fatoum <a.fatoum@pengutronix.de>,
        Marcin Sloniewski <marcin.sloniewski@gmail.com>,
        Rob Herring <robh+dt@kernel.org>, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-stm32@st-md-mailman.stormreply.com
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The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output.
stm32mp15-pinctrl.dtsi contains one pin state definition for the DCMI
interface, dcmi-0, AKA phandle dcmi_pins_a. This definition is
incompatible with the pins used on the Odyssey board, where:
- there are 8 data pins instead of 12,
- DCMI_HSYNC is available at PA4 instead of PH8,
- DCMI_D0 is at PC6 instead of PH9,
- DCMI_D3 is at PE1 instead of PH12,
- DCMI_D4 is at PE11 instead of PH14,
- DCMI_D5 is at PD3 instead of PI4,
- DCMI_D6 is at PE13 instead of PB8,
- DCMI_D7 is at PB9 instead of PE6.

Override the dcmi_pins_a definition (as well as dcmi_sleep_pins_a) in
the Odyssey device tree.

Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl>
---
 arch/arm/boot/dts/stm32mp157c-odyssey.dts | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
index be1dd5e9e744..2d6cf70ca623 100644
--- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts
+++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
@@ -22,6 +22,38 @@ chosen {
 	};
 };
 
+&dcmi_pins_a {
+	pins {
+		pinmux = <STM32_PINMUX('A', 4,  AF13)>,/* DCMI_HSYNC */
+			 <STM32_PINMUX('B', 7,  AF13)>,/* DCMI_VSYNC */
+			 <STM32_PINMUX('A', 6,  AF13)>,/* DCMI_PIXCLK */
+			 <STM32_PINMUX('C', 6,  AF13)>,/* DCMI_D0 */
+			 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
+			 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
+			 <STM32_PINMUX('E', 1,  AF13)>,/* DCMI_D3 */
+			 <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
+			 <STM32_PINMUX('D', 3,  AF13)>,/* DCMI_D5 */
+			 <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
+			 <STM32_PINMUX('B', 9,  AF13)>;/* DCMI_D7 */
+	};
+};
+
+&dcmi_sleep_pins_a {
+	pins {
+		pinmux = <STM32_PINMUX('A', 4,  ANALOG)>,/* DCMI_HSYNC */
+			 <STM32_PINMUX('B', 7,  ANALOG)>,/* DCMI_VSYNC */
+			 <STM32_PINMUX('A', 6,  ANALOG)>,/* DCMI_PIXCLK */
+			 <STM32_PINMUX('C', 6,  ANALOG)>,/* DCMI_D0 */
+			 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
+			 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
+			 <STM32_PINMUX('E', 1,  ANALOG)>,/* DCMI_D3 */
+			 <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
+			 <STM32_PINMUX('D', 3,  ANALOG)>,/* DCMI_D5 */
+			 <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
+			 <STM32_PINMUX('B', 9,  ANALOG)>;/* DCMI_D7 */
+	};
+};
+
 &ethernet0 {
 	status = "okay";
 	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
-- 
2.30.2