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From:   Nava kishore Manne <navam@xilinx.com>
To:     Rob Herring <robh@kernel.org>
CC:     Michal Simek <michals@xilinx.com>,
        "mdf@kernel.org" <mdf@kernel.org>,
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        "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
        Amit Sunil Dhamne <amitsuni@xlnx.xilinx.com>,
        Tejas Patel <tejasp@xlnx.xilinx.com>,
        "zou_wei@huawei.com" <zou_wei@huawei.com>,
        Sai Krishna Potthuri <lakshmis@xilinx.com>,
        Ravi Patel <RAVIPATE@xilinx.com>,
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        Jiaying Liang <jliang@xilinx.com>,
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        git <git@xilinx.com>,
        "chinnikishore369@gmail.com" <chinnikishore369@gmail.com>
Subject: RE: [PATCH v6 3/4] dt-bindings: firmware: Add bindings for xilinx
 firmware
Thread-Topic: [PATCH v6 3/4] dt-bindings: firmware: Add bindings for xilinx
 firmware
Thread-Index: AQHXTU+iEF35WlZWCE+RLpdahH4hlKsBIGSAgAJsNQA=
Date:   Fri, 4 Jun 2021 07:36:53 +0000
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References: <20210520080954.1393-1-nava.manne@xilinx.com>
 <20210520080954.1393-4-nava.manne@xilinx.com>
 <20210602183131.GA3706177@robh.at.kernel.org>
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Hi Rob,

	Thanks for providing the review comments.
Please find my response inline.

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Thursday, June 3, 2021 12:02 AM
> To: Nava kishore Manne <navam@xilinx.com>
> Cc: Michal Simek <michals@xilinx.com>; mdf@kernel.org; trix@redhat.com;
> arnd@arndb.de; Rajan Vaja <RAJANV@xilinx.com>;
> gregkh@linuxfoundation.org; Amit Sunil Dhamne
> <amitsuni@xlnx.xilinx.com>; Tejas Patel <tejasp@xlnx.xilinx.com>;
> zou_wei@huawei.com; Sai Krishna Potthuri <lakshmis@xilinx.com>; Ravi
> Patel <RAVIPATE@xilinx.com>; iwamatsu@nigauri.org; Jiaying Liang
> <jliang@xilinx.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> fpga@vger.kernel.org; git <git@xilinx.com>; chinnikishore369@gmail.com
> Subject: Re: [PATCH v6 3/4] dt-bindings: firmware: Add bindings for xilin=
x
> firmware
>=20
> On Thu, May 20, 2021 at 01:39:53PM +0530, Nava kishore Manne wrote:
> > Add documentation to describe Xilinx firmware driver bindings.
> > Firmware driver provides an interface to firmware APIs.
> > Interface APIs can be used by any driver to communicate to Platform
> > Management Unit.
> >
> > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> > ---
> > Changes for v4:
> >                 -Added new yaml file for xilinx firmware
> >                  as suggested by Rob.
> > Changes for v5:
> >                 -Fixed some minor issues and updated the fpga node name=
 to
> versal_fpga.
> >
> > Changes for v6:
> >                -Added AES and Clk nodes as a sub nodes to the firmware =
node.
> >
> >  .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 102
> > ++++++++++++++++++
> >  1 file changed, 102 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmware
> > .yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmwa
> > re.yaml
> > b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-
> firmwa
> > re.yaml
> > new file mode 100644
> > index 000000000000..58016191e150
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-fi
> > +++ rmware.yaml
> > @@ -0,0 +1,102 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.ya
> > +ml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx firmware driver
> > +
> > +maintainers:
> > +  - Nava kishore Manne <nava.manne@xilinx.com>
> > +
> > +description:
> > +  The zynqmp-firmware node describes the interface to platform
> firmware.
> > +  ZynqMP has an interface to communicate with secure firmware.
> > +Firmware
> > +  driver provides an interface to firmware APIs. Interface APIs can
> > +be
> > +  used by any driver to communicate to PMUFW(Platform Management
> Unit).
> > +  These requests include clock management, pin control, device
> > +control,
> > +  power management service, FPGA service and other platform
> > +management
> > +  services.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - description:
> > +          For implementations complying for Zynq Ultrascale+ MPSoC.
> > +        const: xlnx,zynqmp-firmware
> > +
> > +      - description:
> > +          For implementations complying for Versal.
> > +        const: xlnx,versal-firmware
> > +
> > +  method:
> > +    description: |
> > +                 The method of calling the PM-API firmware layer.
> > +                 Permitted values are.
> > +                 - "smc" : SMC #0, following the SMCCC
> > +                 - "hvc" : HVC #0, following the SMCCC
> > +
> > +    $ref: /schemas/types.yaml#/definitions/string-array
> > +    enum:
> > +      - smc
> > +      - hvc
> > +
> > +patternProperties:
> > +  "versal_fpga":
>=20
> This says 'fooversal_fpgabar' is a valid node name.
>=20
> You don't need a pattern, move under 'properties'. Same for the other chi=
ld
> nodes.
>=20

Will fix in v7.

> > +    $ref: "../../fpga/xlnx,versal-fpga.yaml#"
>=20
> /schemas/fpga/...
>=20
> Don't need quotes.
>=20

Will fix in v7.

> > +    description: Compatible of the FPGA device.
> > +    type: object
> > +    required:
> > +      - compatible
>=20
> Drop. What's required should be in xlnx,versal-fpga.yaml.
>=20

Will fix in v7.

> > +
> > +  "zynqmp-aes":
>=20
> Same comments as above on the rest of the child nodes.
>=20

Will fix in v7.

> > +    $ref: "../../crypto/xlnx,zynqmp-aes.yaml#"
> > +    description: |
> > +                 The ZynqMP AES-GCM hardened cryptographic accelerator=
 is
> > +                 used to encrypt or decrypt the data with provided key=
 and
> > +                 initialization vector.
> > +    type: object
> > +    required:
> > +      - compatible
> > +
> > +  "clock-controller":
> > +    $ref: "../../clock/xlnx,versal-clk.yaml#"
> > +    description: |
> > +                 The clock controller is a hardware block of Xilinx ve=
rsal
> > +                 clock tree. It reads required input clock frequencies=
 from
> > +                 the devicetree and acts as clock provider for all clo=
ck
> > +                 consumers of PS clocks.list of clock specifiers which=
 are
> > +                 external input clocks to the given clock controller.
> > +    type: object
> > +    required:
> > +      - compatible
> > +      - "#clock-cells"
> > +      - clocks
> > +      - clock-names
> > +
> > +required:
> > +  - compatible
> > +
> > +examples:
> > +  - |
> > +    versal-firmware {
> > +      compatible =3D "xlnx,versal-firmware";
> > +      method =3D "smc";
> > +
> > +      versal_fpga: versal_fpga {
> > +        compatible =3D "xlnx,versal-fpga";
> > +      };
> > +
> > +      xlnx_aes: zynqmp-aes {
> > +        compatible =3D "xlnx,zynqmp-aes";
> > +      };
> > +
> > +      versal_clk: clock-controller {
> > +        #clock-cells =3D <1>;
> > +        compatible =3D "xlnx,versal-clk";
> > +        clocks =3D <&ref>, <&alt_ref>, <&pl_alt_ref>;
> > +        clock-names =3D "ref", "alt_ref", "pl_alt_ref";
> > +      };
> > +    };
> > +
> > +additionalProperties: false
>=20
> Move this before the example.

Will fix in v7.

Regards,
Navakishore.