Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp905312pxj; Fri, 4 Jun 2021 00:47:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwFDUx5h1f5YNAiiNU/qWmU0Vu9LimHR0jl8rbboYZa2HVoqGbwiW9sKqmmpyF/xyU77S6E X-Received: by 2002:a05:6402:16db:: with SMTP id r27mr3207856edx.375.1622792869133; Fri, 04 Jun 2021 00:47:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1622792869; cv=none; d=google.com; s=arc-20160816; b=CKPB4ygdV/ZoqMIFvFAzWXd+XFbMxwQV1+4relZ1HU+pDgbgZfWNxQnfPT6DHmIDfS +1ktuqwqkpYR9ot7uL6bIc5p4Is6bg+Dh9cnUJSCnGn0I/80L+BvGHz36JAnuB1zSHCR TtktBVI+tFiKlNMkHNWRgs0NkLAWUn7O9UQj83UncqDROU6v6BgSyfAEfo0FvJVM2hcE 2Ykkvs5LaXS5KAWsj+XEg5naJLdFEf2sJqYIR0s0eXiQaPo8vAIQe1sTQT3gPu56QqII d7B2zi9Cb2ESquBGRqoV18cjOVVHTHMNnzl4KbL7mkbCW/v9HcxSPdxSTV7eIaK6ZmNO Qztw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=XcUqWQkRKGbhFf/RqvB2wJO7PWtSvbYHaKJ3v6/GXNQ=; b=IhSRJj7jTGVlx1K83MtRnl9s9nXQPkO+JTbs7oSGsEeiIm36PidAE2kcd4BvbjIIbJ kZXEtMMFz+AsWesllXFe0VGacIuOuoeUeTjDEOo1OVVCWytlPulRpchr31ngydKcOBM9 LwOJJ7s43/sxrjzudow0LODiVkw+Dmi8m6ASQaJNDReGAxly5+onxAcFbBTTnx7za/Hn Se5YCOMsqMxj1YAgzdFED6IYMX7YdJroaa5I8OPXFZ/3MHcPFQglM0BbWRiYtZMrUOV/ vBRjGQNfH3MEvClCdiLHepkUX1ti87V1pWApbk1AwLgGZspppHjnM3PKTn+KK3dsgKEg iEig== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j11si978916ejj.683.2021.06.04.00.47.24; Fri, 04 Jun 2021 00:47:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230185AbhFDHpk (ORCPT + 99 others); Fri, 4 Jun 2021 03:45:40 -0400 Received: from muru.com ([72.249.23.125]:36152 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229958AbhFDHpj (ORCPT ); Fri, 4 Jun 2021 03:45:39 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id E17AE8167; Fri, 4 Jun 2021 07:43:58 +0000 (UTC) Date: Fri, 4 Jun 2021 10:43:48 +0300 From: Tony Lindgren To: Sven Peter Cc: Rob Herring , devicetree@vger.kernel.org, linux-clk , linux-arm-kernel , "linux-kernel@vger.kernel.org" , Hector Martin , Michael Turquette , Stephen Boyd , Mark Kettenis , Arnd Bergmann Subject: Re: [PATCH 0/3] Apple M1 clock gate driver Message-ID: References: <20210524182745.22923-1-sven@svenpeter.dev> <9ff6ec26-4b78-4684-9c23-16d5cbfef857@www.fastmail.com> <1ff54382-7137-49d6-841d-318e400e956e@www.fastmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1ff54382-7137-49d6-841d-318e400e956e@www.fastmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, * Sven Peter [210603 12:56]: > Another possibility this made me think of is to instead just use the clocks > property the way it's usually used and simply refer to the controller itself, e.g. > > #define APPLE_CLK_UART0 0x270 > #define APPLE_CLK_UART_P 0x220 > #define APPLE_CLK_SIO 0x1c0 > > pmgr0: clock-controller@23b700000 { > compatible = "apple,t8103-gate-clock"; > #clock-cells = <1>; > reg = <0x2 0x3b700000 0x0 0x4000>; > clock-indices = , , ; > clock-output-names = "clock-sio", "clock-uart-", "clock-uart0"; > clocks = <&some_dummy_root_clock>, <&pmgr0 APPLE_CLK_SIO>, > <&pmgr0 APPLE_CLK_UART_P>; > }; How about the following where you set up the gate clocks as separate child nodes: pmgr0: clock-controller@23b700000 { compatible = "apple,foo-clock-controller"; #clock-cells = <1>; reg = <0x2 0x3b700000 0x0 0x4000>; clk_uart0: clock@270 { compatible = "apple,t8103-gate-clock"; #clock-cells = <0>; assigned-clock-parents = <&pmgr0 APPLE_CLK_SIO>, <&pmgr0 APPLE_CLK_UART_P>; // ... }; }; Keep the clock controller still addressable by offset from base as discussed, and additionally have the driver parse and set up the child node clocks. Then I think the consumer driver can just do: serial0: serial@235200000 { // ... clocks = <&clk_uart0>, <&clk24>; clock-names = "uart", "clk_uart_baud0"; // ... }; Regards, Tony