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From:   Vladimir Oltean <vladimir.oltean@nxp.com>
To:     Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
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Subject: Re: [RESEND PATCH net-next v5 3/3] net: stmmac: enable Intel mGbE
 2.5Gbps link speed
Thread-Topic: [RESEND PATCH net-next v5 3/3] net: stmmac: enable Intel mGbE
 2.5Gbps link speed
Thread-Index: AQHXWTET3T5a2O/zYUCUCpJQSG2BQasDwK6A
Date:   Fri, 4 Jun 2021 12:02:48 +0000
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On Fri, Jun 04, 2021 at 06:57:33PM +0800, Michael Sit Wei Hong wrote:
> From: Voon Weifeng <weifeng.voon@intel.com>
>=20
> The Intel mGbE supports 2.5Gbps link speed by increasing the clock rate b=
y
> 2.5 times of the original rate. In this mode, the serdes/PHY operates at =
a
> serial baud rate of 3.125 Gbps and the PCS data path and GMII interface o=
f
> the MAC operate at 312.5 MHz instead of 125 MHz.
>=20
> For Intel mGbE, the overclocking of 2.5 times clock rate to support 2.5G =
is
> only able to be configured in the BIOS during boot time. Kernel driver ha=
s
> no access to modify the clock rate for 1Gbps/2.5G mode. The way to
> determined the current 1G/2.5G mode is by reading a dedicated adhoc
> register through mdio bus. In short, after the system boot up, it is eith=
er
> in 1G mode or 2.5G mode which not able to be changed on the fly.
>=20
> Compared to 1G mode, the 2.5G mode selects the 2500BASEX as PHY interface=
 and
> disables the xpcs_an_inband. This is to cater for some PHYs that only
> supports 2500BASEX PHY interface with no autonegotiation.
>=20
> v2: remove MAC supported link speed masking
> v3: Restructure  to introduce intel_speed_mode_2500() to read serdes regi=
sters
>     for max speed supported and select the appropritate configuration.
>     Use max_speed to determine the supported link speed mask.
>=20
> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
> Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
> ---

Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>=