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[64.180.180.231]) by smtp.gmail.com with ESMTPSA id l3sm9378758pgb.77.2021.06.07.09.48.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Jun 2021 09:48:21 -0700 (PDT) Subject: Re: [PATCH 2/2] PCI: iproc: Support multi-MSI only on uniprocessor kernel To: Sandor Bodo-Merle , Lorenzo Pieralisi , Rob Herring , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Marc Zyngier References: <20210606123044.31250-1-sbodomerle@gmail.com> <20210606123044.31250-2-sbodomerle@gmail.com> From: Ray Jui Message-ID: <927a977c-5bd5-3df1-c990-d817b0759654@broadcom.com> Date: Mon, 7 Jun 2021 09:48:21 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210606123044.31250-2-sbodomerle@gmail.com> Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="00000000000030d35205c42fcf0a" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --00000000000030d35205c42fcf0a Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 6/6/2021 5:30 AM, Sandor Bodo-Merle wrote: > The interrupt affinity scheme used by this driver is incompatible with > multi-MSI as it implies moving the doorbell address to that of another MSI > group. This isn't possible for multi-MSI, as all the MSIs must have the > same doorbell address. As such it is restricted to systems with a single > CPU. > > Fixes: fc54bae28818 ("PCI: iproc: Allow allocation of multiple MSIs") > Reported-by: Marc Zyngier > Signed-off-by: Sandor Bodo-Merle > --- > drivers/pci/controller/pcie-iproc-msi.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-iproc-msi.c b/drivers/pci/controller/pcie-iproc-msi.c > index 557d93dcb3bc..81b4effeb130 100644 > --- a/drivers/pci/controller/pcie-iproc-msi.c > +++ b/drivers/pci/controller/pcie-iproc-msi.c > @@ -171,7 +171,7 @@ static struct irq_chip iproc_msi_irq_chip = { > > static struct msi_domain_info iproc_msi_domain_info = { > .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | > - MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, > + MSI_FLAG_PCI_MSIX, > .chip = &iproc_msi_irq_chip, > }; > > @@ -250,6 +250,9 @@ static int iproc_msi_irq_domain_alloc(struct irq_domain *domain, > struct iproc_msi *msi = domain->host_data; > int hwirq, i; > > + if (msi->nr_cpus > 1 && nr_irqs > 1) > + return -EINVAL; > + This should never happen since the framework would have guarded against this. But I guess it does not hurt to have the check here. > mutex_lock(&msi->bitmap_lock); > > /* > @@ -540,6 +543,9 @@ int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node) > mutex_init(&msi->bitmap_lock); > msi->nr_cpus = num_possible_cpus(); > > + if (msi->nr_cpus == 1) > + iproc_msi_domain_info.flags |= MSI_FLAG_MULTI_PCI_MSI; > + > msi->nr_irqs = of_irq_count(node); > if (!msi->nr_irqs) { > dev_err(pcie->dev, "found no MSI GIC interrupt\n"); > Looks fine to me. Thanks. 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