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[64.180.180.231]) by smtp.gmail.com with ESMTPSA id z17sm8587106pfq.218.2021.06.07.09.45.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Jun 2021 09:45:49 -0700 (PDT) Subject: Re: [PATCH 1/2] PCI: iproc: fix the base vector number allocation for multi-MSI To: Sandor Bodo-Merle , Lorenzo Pieralisi , Rob Herring , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?Q?Pali_Roh=c3=a1r?= References: <20210606123044.31250-1-sbodomerle@gmail.com> From: Ray Jui Message-ID: <89d35f7f-48b2-e117-d7b3-b1ccdec30b4e@broadcom.com> Date: Mon, 7 Jun 2021 09:45:47 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210606123044.31250-1-sbodomerle@gmail.com> Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="00000000000025d07005c42fc6fe" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --00000000000025d07005c42fc6fe Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit On 6/6/2021 5:30 AM, Sandor Bodo-Merle wrote: > Commit fc54bae28818 ("PCI: iproc: Allow allocation of multiple MSIs") > introduced multi-MSI support with a broken allocation mechanism (it failed > to reserve the proper number of bits from the inner domain). Natural > alignment of the base vector number was also not guaranteed. > > Fixes: fc54bae28818 ("PCI: iproc: Allow allocation of multiple MSIs") > Reported-by: Pali Rohár > Signed-off-by: Sandor Bodo-Merle > --- > drivers/pci/controller/pcie-iproc-msi.c | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) > > diff --git a/drivers/pci/controller/pcie-iproc-msi.c b/drivers/pci/controller/pcie-iproc-msi.c > index eede4e8f3f75..557d93dcb3bc 100644 > --- a/drivers/pci/controller/pcie-iproc-msi.c > +++ b/drivers/pci/controller/pcie-iproc-msi.c > @@ -252,18 +252,18 @@ static int iproc_msi_irq_domain_alloc(struct irq_domain *domain, > > mutex_lock(&msi->bitmap_lock); > > - /* Allocate 'nr_cpus' number of MSI vectors each time */ > - hwirq = bitmap_find_next_zero_area(msi->bitmap, msi->nr_msi_vecs, 0, > - msi->nr_cpus, 0); > - if (hwirq < msi->nr_msi_vecs) { > - bitmap_set(msi->bitmap, hwirq, msi->nr_cpus); > - } else { > - mutex_unlock(&msi->bitmap_lock); > - return -ENOSPC; > - } > + /* > + * Allocate 'nr_irqs' multiplied by 'nr_cpus' number of MSI vectors > + * each time > + */ > + hwirq = bitmap_find_free_region(msi->bitmap, msi->nr_msi_vecs, > + order_base_2(msi->nr_cpus * nr_irqs)); > > mutex_unlock(&msi->bitmap_lock); > > + if (hwirq < 0) > + return -ENOSPC; > + > for (i = 0; i < nr_irqs; i++) { > irq_domain_set_info(domain, virq + i, hwirq + i, > &iproc_msi_bottom_irq_chip, > @@ -284,7 +284,8 @@ static void iproc_msi_irq_domain_free(struct irq_domain *domain, > mutex_lock(&msi->bitmap_lock); > > hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq); > - bitmap_clear(msi->bitmap, hwirq, msi->nr_cpus); > + bitmap_release_region(msi->bitmap, hwirq, > + order_base_2(msi->nr_cpus * nr_irqs)); > > mutex_unlock(&msi->bitmap_lock); > > Looks good to me too. Thanks. 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