Received: by 2002:a05:6a10:206:0:0:0:0 with SMTP id 6csp3974290pxj; Tue, 8 Jun 2021 03:30:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwUiKHmttXYylE8nz8JM9Zp4wax7ny1wiXOoKcwKE5ZkSvco1jRn5KXD2LJFW1qtbhouUQY X-Received: by 2002:a17:907:2074:: with SMTP id qp20mr22552954ejb.35.1623148207977; Tue, 08 Jun 2021 03:30:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623148207; cv=none; d=google.com; s=arc-20160816; b=cGC1pAT7iDzpjjVjYp4t9R4PlDFu+bc2T5znGb5JtCzDile+0iIn9qErvGyum3FEJW 2ePwa7H3cjjqSIX8iX3gL/c0R2bDd3G5j6c1dv3k8lAzRugeD+BuCdeBnUhyW6ZqNasR 1BRc3vISjsiotiuGQCEsjIfic8mtPOrp5oqdEoZxc8BA/8qZyMJ1eX+IU3TWulVdPIU5 d+c1UhBWv8DkzWZ3bND6S5aEBMU1k4cs3KtUvG128y2yWFuXww6jQjActTP3lgS+e5JA ZWlECTYQeDaw4mZyqTIHb5ciTSdwjwogIkHJU9Q3gAuSkIHvZYpvSB55HY3oVeDYOxOX mk1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=UhJJC6WHs4ZpsrIlCEmn9BL3/MSzfbJ7NvHcDq61e1g=; b=whNWADgC4tsWGnjEt/9yxfBsiUJcNsuKVKa33Y0u0RQH385k7ZdLONcvc6Z5mxguxC W/s2PyAjrFWHJPZQ6SLCmxaGHhdB6BhidCfNxL1Izoxt1gmfT5jpzAglk6dEExX5pEsq QkqPyVCZj9YHoui2vYPZwv8WAOoUgBhWxQsRM8XdT48gc1oibvDYWK90rUFsObELw4Jh vB6rscrUz/IQiQSGDbkTW/wtFCFk6s+CPRtw+EEr35AWsm5dG9VYUsCpsfVzRA9CEG4k gcvjOyPdVeC/u0sHMN067hiLS5khAAPUegrwDdVXaRg06RwiFMbT9/X8mZWaD3e5djJX n+dA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h5si13231604ede.305.2021.06.08.03.29.45; Tue, 08 Jun 2021 03:30:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231488AbhFHK2W (ORCPT + 99 others); Tue, 8 Jun 2021 06:28:22 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:22524 "EHLO twspam01.aspeedtech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231461AbhFHK2V (ORCPT ); Tue, 8 Jun 2021 06:28:21 -0400 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 158ACCBB009902; Tue, 8 Jun 2021 18:12:12 +0800 (GMT-8) (envelope-from steven_lee@aspeedtech.com) Received: from slee-VirtualBox.localdomain (192.168.100.253) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Jun 2021 18:26:01 +0800 From: Steven Lee To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Joel Stanley , Andrew Jeffery , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , open list CC: , , , Subject: [PATCH v5 07/10] gpio: gpio-aspeed-sgpio: Add set_config function Date: Tue, 8 Jun 2021 18:25:42 +0800 Message-ID: <20210608102547.4880-8-steven_lee@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210608102547.4880-1-steven_lee@aspeedtech.com> References: <20210608102547.4880-1-steven_lee@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.100.253] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 158ACCBB009902 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AST SoC supports *retain pin state* function when wdt reset. The patch adds set_config function for handling sgpio reset tolerance register. Signed-off-by: Steven Lee Reviewed-by: Andrew Jeffery --- drivers/gpio/gpio-aspeed-sgpio.c | 54 +++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c index 7d0a4f6fd9d1..31475846c5fc 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -39,9 +39,10 @@ struct aspeed_sgpio { }; struct aspeed_sgpio_bank { - uint16_t val_regs; - uint16_t rdata_reg; - uint16_t irq_regs; + u16 val_regs; + u16 rdata_reg; + u16 irq_regs; + u16 tolerance_regs; const char names[4][3]; }; @@ -57,24 +58,28 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = { .val_regs = 0x0000, .rdata_reg = 0x0070, .irq_regs = 0x0004, + .tolerance_regs = 0x0018, .names = { "A", "B", "C", "D" }, }, { .val_regs = 0x001C, .rdata_reg = 0x0074, .irq_regs = 0x0020, + .tolerance_regs = 0x0034, .names = { "E", "F", "G", "H" }, }, { .val_regs = 0x0038, .rdata_reg = 0x0078, .irq_regs = 0x003C, + .tolerance_regs = 0x0050, .names = { "I", "J", "K", "L" }, }, { .val_regs = 0x0090, .rdata_reg = 0x007C, .irq_regs = 0x0094, + .tolerance_regs = 0x00A8, .names = { "M", "N", "O", "P" }, }, }; @@ -87,6 +92,7 @@ enum aspeed_sgpio_reg { reg_irq_type1, reg_irq_type2, reg_irq_status, + reg_tolerance, }; #define GPIO_VAL_VALUE 0x00 @@ -115,6 +121,8 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio, return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; case reg_irq_status: return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; + case reg_tolerance: + return gpio->base + bank->tolerance_regs; default: /* acturally if code runs to here, it's an error case */ BUG(); @@ -476,6 +484,44 @@ static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = { .pin_mask = GENMASK(9, 6), }; +static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip, + unsigned int offset, bool enable) +{ + struct aspeed_sgpio *gpio = gpiochip_get_data(chip); + unsigned long flags; + void __iomem *reg; + u32 val; + + reg = bank_reg(gpio, to_bank(offset, gpio), reg_tolerance); + + spin_lock_irqsave(&gpio->lock, flags); + + val = readl(reg); + + if (enable) + val |= GPIO_BIT(gpio, offset); + else + val &= ~GPIO_BIT(gpio, offset); + + writel(val, reg); + + spin_unlock_irqrestore(&gpio->lock, flags); + + return 0; +} + +static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + unsigned long param = pinconf_to_config_param(config); + u32 arg = pinconf_to_config_argument(config); + + if (param == PIN_CONFIG_PERSIST_STATE) + return aspeed_sgpio_reset_tolerance(chip, offset, arg); + + return -ENOTSUPP; +} + static const struct aspeed_sgpio_pdata ast2600_sgpiom_128_pdata = { .max_ngpios = 128, .pin_mask = GENMASK(10, 6), @@ -577,7 +623,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev) gpio->chip.free = NULL; gpio->chip.get = aspeed_sgpio_get; gpio->chip.set = aspeed_sgpio_set; - gpio->chip.set_config = NULL; + gpio->chip.set_config = aspeed_sgpio_set_config; gpio->chip.label = dev_name(&pdev->dev); gpio->chip.base = -1; -- 2.17.1