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Subject: Re: [PATCH V2 2/5] PCI: tegra: Fix MSI-X programming
To:     Om Prakash Singh <omp@nvidia.com>, <kw@linux.com>,
        <helgaas@kernel.org>, <lorenzo.pieralisi@arm.com>,
        <bhelgaas@google.com>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>
CC:     <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <kthota@nvidia.com>,
        <mmaddireddy@nvidia.com>
References: <20210606082204.14222-1-omp@nvidia.com>
 <20210606082204.14222-3-omp@nvidia.com>
From:   Vidya Sagar <vidyas@nvidia.com>
Message-ID: <c0d4b6bd-d521-191b-6fb6-50ba4c89df51@nvidia.com>
Date:   Tue, 8 Jun 2021 16:07:48 +0530
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Acked-by: Vidya Sagar <vidyas@nvidia.com>

On 6/6/2021 1:52 PM, Om Prakash Singh wrote:
> Lower order MSI-X address is programmed in MSIX_ADDR_MATCH_HIGH_OFF
> DBI register instead of higher order address. This patch fixes this
> programming mistake.
> 
> Signed-off-by: Om Prakash Singh <omp@nvidia.com>
> ---
> 
> Changes in V2:
> 	- No change
> 
>   drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 6f388523bffe..66e00b276cd3 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1863,7 +1863,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>   	val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
>   	val |= MSIX_ADDR_MATCH_LOW_OFF_EN;
>   	dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val);
> -	val = (lower_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
> +	val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
>   	dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);
>   
>   	ret = dw_pcie_ep_init_complete(ep);
>