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Date:   Wed, 9 Jun 2021 14:05:21 +0800
From:   Jisheng Zhang <Jisheng.Zhang@synaptics.com>
To:     Guo Ren <guoren@kernel.org>
Cc:     Nick Kossifidis <mick@ics.forth.gr>,
        Christoph Hellwig <hch@lst.de>,
        Drew Fustini <drew@beagleboard.org>,
        Anup Patel <anup.patel@wdc.com>,
        Palmer Dabbelt <palmerdabbelt@google.com>, wefu@redhat.com,
        "Wei Wu ( =?UTF-8?B?5ZC05Lyf?=)" <lazyparser@gmail.com>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-arch <linux-arch@vger.kernel.org>,
        linux-sunxi@lists.linux.dev, Guo Ren <guoren@linux.alibaba.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Benjamin Koch <snowball@c3pb.de>,
        Matteo Croce <mcroce@linux.microsoft.com>,
        Wei Fu <tekkamanninja@gmail.com>
Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support
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On Wed, 9 Jun 2021 11:28:19 +0800
Guo Ren <guoren@kernel.org> wrote:


>=20
>=20
> On Mon, Jun 7, 2021 at 2:14 AM Nick Kossifidis <mick@ics.forth.gr> wrote:
> >
> > =CE=A3=CF=84=CE=B9=CF=82 2021-05-20 04:45, Guo Ren =CE=AD=CE=B3=CF=81=
=CE=B1=CF=88=CE=B5: =20
> > > On Wed, May 19, 2021 at 2:53 PM Christoph Hellwig <hch@lst.de> wrote:=
 =20
> > >>
> > >> On Tue, May 18, 2021 at 11:44:35PM -0700, Drew Fustini wrote: =20
> > >> > This patch series looks like it might be useful for the StarFive J=
H7100
> > >> > [1] [2] too as it has peripherals on a non-coherent interconnect. =
GMAC,
> > >> > USB and SDIO require that the L2 cache must be manually flushed af=
ter
> > >> > DMA operations if the data is intended to be shared with U74 cores=
 [2]. =20
> > >>
> > >> Not too much, given that the SiFive lineage CPUs have an uncached
> > >> window, that is a totally different way to allocate uncached memory.=
 =20
> > > It's a very big MIPS smell. What's the attribute of the uncached
> > > window? (uncached + strong-order/ uncached + weak, most vendors still
> > > use AXI interconnect, how to deal with a bufferable attribute?) In
> > > fact, customers' drivers use different ways to deal with DMA memory i=
n
> > > non-coherent SOC. Most riscv SOC vendors are from ARM, so giving them
> > > the same way in DMA memory is a smart choice. So using PTE attributes
> > > is more suitable.
> > >

<snip>

> > > 4.4.1
> > > The draft supports custom attribute bits in PTE.
> > > =20
> >
> > Not only it doesn't support custom attributes on PTEs:
> >
> > "Bits63=E2=80=9354 are reserved for future standard use and must be zer=
oed by
> > software for forward compatibility."
> >
> > It also goes further to say that:
> >
> > "if any of these bits are set, a page-fault exception is raised" =20
> Agree, when our processor's mmu works in compatible mmu, we must keep
> "Bits63=E2=80=9354 bit" zero in Linux.
> So, I think this is the first version of the PTE format.
>=20
> If the "PBMT" extension proposal is approved, it will cause the second
> version of the PTE format.
>=20
> Maybe in the future, we'll get more versions of the PTE formats.
>=20
> So, seems Linux must support multi versions of PTE formats with one
> Image, right?
>=20
> Okay, we could stop arguing with the D1 PTE format. And talk about how
> to let Linux support multi versions of PTE formats that come from the
> future RISC-V privilege spec.
>=20

Just my humble opinion:
When those bits(63~54) usage are standardized in future RISC-V privilege sp=
ec
generic Image can still be supported with the following solutions:

*alternative patch only fly:
If the bit is only need to be set during init, we may insert nop instructio=
n(s)
at proper place, then patch the nop into set_the_target_bit instruction(s) =
by
hart's feature.

*normal check feature then use:
If the feature needs a bit complex code, we could go through the "feature c=
heck
then use". static key tech can be used here to avoid branches.